1402 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016 An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS Yang Zhao, Yilei Shen, Pan Xue, Zhiwei Ma, Zhenfei Peng, Baoxing Chen, and Zhiliang Hong Abstract—A 65-nm all-digital Class-S transmitter with an entire digital frontend (DFE) and a current-mode Class-D (CMCD) power amplifier (PA) is presented. To realize the high operation rate and performance of the DFE, which includes a 1-bit band-pass  modulator, a mixer, and inter- polation filters, approaches, such as time-interleaving algorithm and modified Manchester encoding, are adopted. The main blocks in the DFE are implemented using standard cells with electronic design automation tools for synthesis and place and route. A CMCD PA with an ON-chip transformer is designed and integrated. This Class-S transmitter exhibits a 40-MHz band- width at up to a 1.6 GHz output carrier frequency. Measurements with a 1-MHz channel-spacing π /4 quadrature phase shift keying signal show a power control range of -18.66 to -4.65 dBm, and the power consumption of the  modulator core is 7 mW. Index Terms—Class-S transmitter, CMOS integrated circuits, Manchester encoding, power amplifiers, sigma–delta modulator, time-interleaving, transformers. I. I NTRODUCTION W HILE size and cost benefits drive the monolithic integration of radio-frequency (RF) transmitters (TXs) with digital blocks like processors, memories, and other digital function blocks, the reduction of available supply voltage swing complicates the migration of traditional RF circuits to advanced CMOS technology. Recently, intensive research has focused on digital-modulated TXs with switched-mode power amplifiers (PAs) that suit for submicrometer CMOS technol- ogy and ease integration. Several system-level solutions have been published, like a digital polar [1], digital out-phasing [2], and Cartesian direct digital topology [3]. As an alternative topology, [4]–[8] have introduced the concept of an all-digital Class-S TX. The basic concept is that using  modulator, a fast 1-bit switching signal is generated conveying both phase Manuscript received February 2, 2015; revised April 30, 2015; accepted May 31, 2015. Date of publication July 8, 2015; date of current version March 18, 2016. This work was supported in part by the National Science Foundation of China under Grant 61376030, in part by the Science and Technology Commission of Shanghai Municipality under Grant 13511501100, and in part by the Analog Devices Inc., Norwood, MA, USA. Y. Zhao, Y. Shen, P. Xue, and Z. Hong are with the State Key Laboratory of ASIC and Systems, Fudan University, Shanghai 201203, China (e-mail: zhao_yang@fudan.edu.cn; ylshen14@fudan.edu.cn; xuepan@fudan.edu.cn; zlhong@fudan.edu.cn). Z. Ma is with Fudan Microelectronics Group Company, Ltd., Shanghai 200433, China (e-mail: mazhiwei@fudan.edu.cn). Z. Peng is with Smarter Microelectronics, Shanghai 201203, China (e-mail: zfpeng@fudan.edu.cn). B. Chen is with Analog Device Inc., Wilmington, MA 01887 USA (e-mail: baoxing.chen@analog.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2015.2446131 and amplitude information. This 1-bit signal is appropriate to drive a switched-mode PA and ensures the PA’s linearity. The TX approach in [4]–[6] consists of two low-pass (LP)  modulators to work on I / Q baseband signals, which are summed in power combination stage. The sampling rate of  modulators in [4] can be up to 4 GHz. Full-custom dynamic logic digital designs have been demonstrated in [4] and [6], their cost, power consumption, and design complexity are not amenable for integration. Reference [6] uses  modulation and pulse-width modulation and integrates switched capacitor PAs. Complex OFF-chip passive components are required in [6] to combine I / Q signals. Another approach is using band-pass (BP)  modulators [7], [8]. Previously published BP Class-S TXs have not demonstrated the integration of the entire system in CMOS circuits and typically have only provided a relatively low frequency (900 MHz in [7] and 1 GHz in [8]) with a narrow bandwidth. This paper demonstrates the feasibility of an all-digital gigahertz Class-S TX based on a BP  modulator, which incorporates a complete system of a digital frontend (DFE) and a current-mode Class-D (CMCD) PA. Main blocks within the DFE are implemented using standard cells and automatic digital synthesis tools. To improve the signal integrity of the PA, an ON-chip transformer is also incorporated. This paper is organized as follows. The Class-S TX archi- tecture is proposed in Section II with system-level design considerations. The implementation of the DFE is unveiled in Section III. Design approaches, such as time-interleaving algorithm and modified Manchester encoding, are used in a DFE to achieve the gigahertz operating speed. In Section IV, the design of CMCD PA is described as well as the matching network. The measurement results are detailed in Section V. II. PROPOSED CLASS-S TX ARCHITECTURE The block diagram of proposed Class-S TX is presented in Fig. 1, which can be partitioned into two parts, namely, the DFE and the PA stage. The DFE provides the 1-bit signal to be amplified by a PA and transmitted at RF. Compared with RF, the sampling rate is usually relatively slow. Cascaded interpolation filters are applied before mixer and  modulator. In this design, sampling rate is trebled first by an inverse finite-impulse response filter and then doubled for 4 times. Tradeoff performance and the hardware cost of a nonsensitive desensitized half-band filter structure [9] is used for LP filters. The digital signals are mixed to RF and quantized to a 1-bit signal by the BP  modulator 1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.