International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 4 (2016) pp 2298-2304 © Research India Publications. http://www.ripublication.com 2298 An Integrated Switching Technique for Minimizing Power Consumption Using MDFSD in Domino Logic System J. Muralidharan Research Scholar, Department of Electronics and Communication Engineering, Karpagam University, Coimbatore, Tamil Nadu, India. Dr. P. Mamimegalai Professor, Department of Electronics and Communication Engineering, Karpagam University, Coimbatore, Tamil Nadu, India. Abstract A domino logic technique is designed to meet the critical concern of the VLSI era with convenience and high microelectronic devices, power consumption of the digital circuit. The design and circuit performance improves the power consumption, area and delay of the circuit. If there is a path delay in wide fan multiplexers, then path reads out becomes more difficult and there is high power consumption due to switching activity, also it has high noise immunity in the dynamic gates. At a lower level, if the device operates with better efficiency the power consumption, speed, delay processing and power dissipation have to be sustained. To maintain the device level proposed circuit design is implemented, so that the voltage level is minimized. The designed Filtered Switch Domino (FSD), Multi Dynamic Node Domino (MDND) and measured the parameters like power, area and delay. For further improvement both the FSD and MDND were combined and results have been deliberate. The experimental setup is designed by Cadence –Virtuoso analogy tools. In domino logic circuit these techniques are proposed to improve the performance and to provide better results in power consumption than the existing methods. Keywords: Keeper and Footer circuit; Critical Path Delay; Dynamic Structure, Domino Logic Introduction For high performance in integrated circuit design, we are implementing clocked logic circuit methodology. It has been designed to provide low-power static random access to various applications. We perform VLSI technology with less energy consumption, the design is implemented to reduce the static process burden and to manage the delay of the logic circuit. Dynamic logic of the device is exploiting from the static logic, which deliberate the information of capacitances in the circuit design. Dynamic logic has been used worldwide for achieving the high performance in VLSI devices. In an increased application of VLSI Technology, operating the appliance with less energy consumption as well as reduced structure is a tedious process nowadays. Multiplexer requires a strong keeper circuits for the compensation techniques. Charge sharing is recovered in many of the previous work but still it creates high heat dissipation along with increased delay in the circuit over the devices. Clocked Logic Circuit is rapid access than the static in counterparts, toggle rate and power consumption. Based on trade-offs, the consumption is defined and the toggle will be smaller in the logic circuit. The methodology of dynamic design is distinguished usually when it refers to logic family like SOI design. In combinational or integrated logic circuit the clocked logic uses the clock signal in sequential form for synchronizing the transitions. Wide fan-in dynamic multiplexers are used to make the critical circuits of read-out paths in high-speed register files. In the existing topologies new Footer Voltage Feed Forward Domino (FVFD) and Static Switching Pulse Domino (SSPD) designs for dynamic multiplexers are used, so that they make the voltage swing at a high manner. Not only increasing the keeper circuit and the Footer circuit in the read path alone can give the solution to charge pump reduction to operate the VLSI circuits but also alternative ways will provide different approaches achieving this process for the charge pump. To overcome the above stated problems, new domino logic is designed from the existing dominos like static domino logic which is a traditional logic system but by having more voltage swing. In the previous topologies, dynamic multiplexers are nearly new to make voltage swing at a high manner with new Footer Voltage Feed Forward Domino (FVFD) and Static Switching Pulse Domino (SSPD) designs. In this paper, dynamic logic system FSD and MDND have been designed to improve the performance analysis of consumption in the VLSI device. In real time applications, generally footer circuits are used for area selection which consists of capacitance voltage improvement. Due to the improvement in voltage, capacitance, area selection is possible in footer circuits. If there are no such possibilities, an area selection process cannot be achieved in the real time applications. In the traditional logic system a new logic circuit is designed from existing dominos which have more voltage swing. New domino logics called Filtered Switch Domino Logic (FSD) and Multi Dynamic Node Domino (MDND) are designed through a transistor level for the correct operations, which provides high speed, dependable operation, which has a smaller area than the static gates and lesser parasitic capacitances, compared to the traditional method, which is in practice. Also low power domino logic circuit techniques were also designed, which can able to control and minimize the leakage current and power delay. The proposed work is