A Novel Design of Modular Adder using NRA and RNA Reversible Logic gates for High speed Application K. Nansy S. Ranjith M,E.VLSI Design, Assistant Professor, Department of ECE, Department of ECE, Jeppiaar Engineering College, Jeppiaar Engineering College, Chennai,India. Chennai,India. Abstract-In digital world need for low power and high speed compatible device has been increased. This has turned the attention towards research in the field of reversible logic gates. This paper deals with the design of modular adder which would speed up the addition process. The use of reversible logic gate had made the design easier. Regularly the Fredkin gate and Feynman gates are used for permutation and copy operation. We propose a design based on the NRA and RNA. The combination of these two gates is called MCRG(memory compressive reversible logic gate) for implementing modular adder which performs a modular operation with reduced hardware complexity. The speed improvement is analyzed and compared with the existing designs using NRA&RNA reversible logic gate. In Proposed design, we have implemented MCRG to have reduced area, delay, speed, and garbage outputs. Keywords: NRA;RNA;,MCR;Modular adder I. INTRODUCTION The reversible logic gate is the one which has an equal number of inputs and outputs. A reversible logic gate totally differs from the normal universal gate. It has the ability to perform every operation as a normal gate and it is easy to implement and design. The two important rules for reversible logic gate: It should be able to produce the output from the input as well as reproduce the input from the output with zero power consumption. The input and output should be capable of being retained and operates in the reverse of the usual direction. Advantages of reversible logic gates are they reduce the power wastage. It connects with the other gates without loops and fanouts. The existing reversible logic gate are Toffoli, Fredkin, Feymann, Peres, NFT, BJN, NG, TSG, F2G, COG, HNG, modified Islam gate,MKG,ALG,DKG etc.., Generally the adders can be divided into half and full adder depending on the number of inputs and the output(sum and carry) is same for both the adder. Different types of the adder in VLSI are Ripple carry adder, Carry save adder, Carry increment adder, Carry select adder, Carry skip adder, Carry look ahead adder, Carry bypass adder and so on. We can classify the modular adder into a general modular adder and special modular adder depending on the form of modules. RNS stands for Residue number system which is used to perform the parallel computation of a system. In normal division, we take quotient as the output but in modulus operation, we take the remainder as the output. For modular RNS, first we should take a number’x’ and then the co-prime number for the given number’x1,x2,x3’ followed by the modulus operation(x/x1,x/x2,x/x3).we will get a module set that is the output of modular RNS operation which will be used for further calculations(addition).In a digital circuit, adders are used for performing a boolean operation using logic gates. In analog, it is used for adding analog voltages. Because of the use of an adder the operating speed is improved. Among several adders carry look ahead adder is the fastest adder. Implementation and design of carry save, carry select and carry skip using proposed NRA, RNA - MCRG gates for modular addition based on RNS is implemented and designed. II. EXISTING SYSTEM A.Available reversible logic gate: Depending on the application/requirement we can choose the type and number of gates. Currently available reversible logic gates are 2×2,3×3,4×4,5×5. Some of them are listed below: A. DKG It is a 4*4 gate which has four input and four output.[2] Fig 1. DKG Inputs for the above gate is 0,A,B,C and Output is P,Q,R,S. B.R-R gate It is a 4*4 gate which has four input and four output.[4] International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 http://www.ijert.org IJERTV8IS050209 (This work is licensed under a Creative Commons Attribution 4.0 International License.) Published by : www.ijert.org Vol. 8 Issue 05, May-2019 328