A Delta Sigma Based Finite Impulse Response Filter for EEG Signal Processing Yifei Liu, Wei Tang Klipsh School of Electrical and Computer Engineering, New Mexico State University wtang@nmsu.edu Abstract— This paper presents the design of a Finite Impulse Response Filter based on Delta Sigma Signal Processing. Both input and output of the proposed circuit are encoded as second- order Delta Sigma bit-streams. The design is realized using a Delta Sigma adder based on an input counter. The Delta Sigma adder can also be used as a coefficient multiplier. Using the proposed Delta Sigma adder and coefficient multiplier, an Finite Impulse Response filter is designed for Electroencephalogram signal processing. Simulation and synthesis results are shown based on IBM 180nm CMOS technology. The proposed design achieves a Θ(N) complexity with N inputs and can work with higher-order Delta Sigma bit-streams. Index Terms—Electroencephalogram (EEG), Delta Sigma Modulation (DSM), Delta Sigma Signal Processing (DSSP), Finite Impulse Response (FIR) filter I. I NTRODUCTION In recent years, there is a growing demand of low power miniaturized digital signal processing (DSP) circuits for wear- able medical devices to process biomedical signals in real time. For example, an Electroencephalogram (EEG) seizure detector with a feature extraction processor can detect or predict seizures using a machine-learning based algorithm [1]. In such applications, accuracy, reliability, circuit size, and power are the most important considerations. Critical design challenges come from the large size and high power consumption of multiply-and-accumulate (MAC) circuits. For example, in the above EEG processor, an 8-channel 48-tap Finite Impulse Response (FIR) filter bank is required with a 12-bit resolution. The multipliers and adders in the FIR filter cost 70% of the chip area and power [2]. Besides, accuracy of the algorithm is limited by the resolution of a front-end analog- to-digital converter (ADC). A Nyquist rate ADC is difficult or costly to reach a resolution above 14-bit. Moreover, once the device is fabricated, the resolution of system is fixed, without a flexibility of further adjusting. A Delta Sigma Signal Processing (DSSP) system has a great potential to tremendously relieve the above design challenges [3]. In a DSSP system, analog inputs are encoded by non- weighted bit-streams using oversampling Delta Sigma Mod- ulators (DSM). A Delta Sigma system has several advan- tages. First, compared to a Nyquist rate ADC, a DSM based oversampling ADC can achieve higher resolution using less circuitry and power [4]. Second, resolution of an oversampling system is adjustable by changing the sampling frequency at the input after fabrication [4]. Third, a DSM system has a higher reliability than a Nyquist rate system since a DSM N-bit Analog to Digital Converter Analog Input Digital Result (a) 1-bit 1-bit Digital Signal Processing Analog Input Digital Result (b) Delta Sigma Modulator N-bit Digital Signal Processing Fig. 1. (a) Nyquist Rate System using N-bit Nyquist rate DSP circuits. (b) Delta Sigma System using the proposed 1-bit Delta Sigma DSP circuits. bit-stream can tolerant higher bit-error-rate (BER) during data communication [5]. Moreover, the multiplier and adder circuits based on Delta Sigma modulation could have much less power and circuit area compared to their Nyquist rate counterparts. A typical Nyquist rate DSP system and a proposed DSSP system are shown in Fig. 1. A Delta Sigma Signal Processing system takes Delta Sigma bit-streams from Delta Sigma Modulators as inputs. The 1-bit width DSM bit-stream is processed by a 1-bit DSSP circuit. Concerns of applying Delta Sigma system focus on the higher oversampling ratio (OSR). However, in biomedical applications such concern is alleviated since biomedical signals usually have a relatively low bandwidth. Although a Delta Sigma processing system has several ad- vantages, currently DSSP designs are not widely implemented because of their limitations. For example, in previous proposed DSSP systems, Delta Sigma adders can only process first-order Delta Sigma bit-streams [6] [7]. Higher-order DSM adders are realized using complicated sorting networks [5], which has a complexity of Θ(Nlog(N)) with N-inputs. This costs too much circuit area and power compared to Nyquist rate systems. Although three types of Delta Sigma FIR filters have been proposed [8] [9], the outputs of these FIR filters are already pulse code modulation (PCM) bits which lose the noise shaping merits of the DSM bit-streams, and can not be further processed by a Delta Sigma based system. This paper proposes a novel Delta Sigma adder using a counter based digital Delta Sigma Modulator. The proposed adder can process higher-order Delta Sigma bit-streams, and has a complexity of only Θ(N) with N-inputs . The adder also can be used as a Delta Sigma coefficient multiplier. Using the adder and the coefficient multiplier, we designed a fully Delta