XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE Multiplexer based voltage controlled delay buffer element Pooja Saxena Electronics and communication Department Greater Noida Institute of Technology Greater Noida, India saxena06pooja@gmail.com Mohd Amir Khan Technical Trainer GLA University Mathura, India amirkhan1092@gmail.com Abstract—this paper presents a voltage controlled delay buffer using a 2:1 multiplexer, designed in 0.35 µm CMOS process. The multiplexer is realized with transmission gate, which results in achievement of high speed, low power and full swing output characteristics of delay buffer. The least attained post layout rising edge delay is 120 ps that is comparable with standard cell inverter. The delay regulation range achieved over control voltage of 0 V to 3.3 V is from 120ps to 560ps. The performance of delay buffer for single edge delay control across PVT variations is successfully verified by design of modified delay lock loop. Keywords— Time-to-Digital Converter (TDC), Current Starved Inverter, Delay Lock Loop (DLL), Process Voltage and Temperature (PVT) Introduction The voltage controlled delay element is a critical part for implementation of time-to-digital converter (TDC) based on the tapped delay line technique [1, 2]. Here, the least delay obtained from delay element of delay line defines the resolution of TDC. To design a delay line based TDC using mixed signal design flow with target resolution of less than 200ps, a high speed (<150 ps), low power (zero static current) and full swing delay element is needed. The full swing of delay element provides a good interfacing with standard cell provided by process design kit. Various types of delay elements have been reported in the literature. The conventional current starved inverter [3, 4] based delay element features simple design, low power (ideally zero static power), wide delay regulation range and full output swing. However, it’s least delay achieved in available resource of 0.35 µm CMOS process is around 400 ps. The Transmission gate based delay element [5] is fast due to relatively low resistive path between input and output. Also, it is power and area efficient and has full output swing. However, in the cascaded delay line, the delay increases quadratically with the number of delay elements [6]. This causes non-linearity in the tapped delays which can be mitigated by using the input signal (clock or step) as a control signal of transmission gate. Based on this concept, a voltage controlled logic buffer using 2:1 multiplexer is designed. The multiplexer itself is implemented using transmission gate, thereby utilizing its above stated features. Thus, a delay buffer with salient features of high speed (120 ps), low power (~ zero static current), full swing ( 0 to 3.3V) and wide delay regulation range (120ps to 560ps) in rising edge is presented in this paper. Also to verify the performance of delay buffer against process voltage and temperature (PVT) variations, a modified delay lock loop (DLL) with single edge delay control is implemented. This paper is organized in the following sections: In section 2, architecture of multiplexer based delay buffer is presented. In section 3, a brief description of DLL blocks and its working with proposed delay buffer has been presented. In Section 4, post layout simulation results are presented. In section 5, conclusions are drawn.. I. MULTIPLEXER BASED VOLTAGE CONTROL DELAY ELEMENT This delay element is based on the realization of logic buffer using 2:1 multiplexer as shown in Fig.1. Here, its selection line is connected to the ‘Vin’ and inputs ‘I0’ and ‘I1’ are connected to supply voltage (Vdd) & ground (gnd) respectively. When ‘Vin’ is high, the output node ‘Vout’ connects to Vdd, thereby pulls up to high state. When Vin is low, Vout connects to gnd thereby pulls down to low. The multiplexer is realized using transmission gate (TM1 and TM2) where, the delay in transmission of Vdd (or gnd) to output node is determined by the time to charge (or discharge) a load capacitance CL through the equivalent resistance Req of two transistors (M1 and M2) connected in parallel. This transmission delay defines the rising and falling edge transition delays of logic buffer. Fig. 1: Logic buffer derived from transmission gate based 2:1 multiplexer Fig. 2: Proposed voltage controlled logic buffer using transmission gate based 2:1 multiplexer