International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 02 | Feb 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1554 Design of Energy Efficient 8T SRAM cell at 90nm Technology M.N. Naga Vyshnavi 1 , S. Mohan Das 2 1 P.G. Student, S.V.R. Engineering College, Nandyal. 2 Associate Professor, S.V.R. Engineering College, Nandyal. ---------------------------------------------------------------------***---------------------------------------------------------------------- Abstract - A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of 1.4× and 1.28× as that of iso-area 6T and read-decoupled 8T (RD-8T), respectively, at 300 mV. The standard deviation of write SNM for 8T cell is reduced as that for 6T and RD-8T, respectively. It also possesses another striking feature of high read SNM as that of 5T, 6T, and RD-8T, respectively. The proposed 8T consumes less write power as that of 5T, 6T, and iso-area RD-8T, respectively. The power/energy consumption of 1-kb 8T SRAM array during read and writes operations minimized. These features enable ultralow power applications of 8T. Key Words: Single ended, static noise margin (SNM), static RAM (SRAM), sub-threshold, ultralow power. 1. INTRODUCTION The growing demand of portable battery operated systems has made energy efficient processors a necessity. For applications like wearable computing energy efficiency takes top most priority. These embedded systems need repeated charging of their batteries. The problem is more severe in the wireless sensor networks which are deployed for monitoring the environmental parameters. These systems may not have access for recharging of batteries. We know that on chip memories determine the power dissipation of SoC chips. Hence it is very important to have low power and energy efficient and stable SRAM which is mainly used for on chip memories. There are various approaches that are adopted to reduce power dissipation, like design of circuits with power supply voltage scaling, power gating and drowsy method. Lower power supply voltage reduces the dynamic power in quadratic fashion and leakage power in exponential way. But power supply voltage scaling results in reduced noise margin. Many SRAM arrays are based on minimizing the active capacitance and reducing the swing voltage. In sub-100nm region leakage currents are mainly due to gate leakage and sub threshold leakage current. High dielectric constant gate technology decreases the gate leakage current. Forward body biasing methods and dual VT techniques are used to reduce sub threshold leakage current. In sub threshold SRAMs power supply voltage (VDD) is lower than the transistor threshold voltage (VT) and the sub threshold leakage current is the operating current. The energy loss during writing is more than the energy loss during reading in conventional SRAM since there is full swing of voltage in bit lines whereas the bit line voltage swing is very less during reading. It is known that the energy stored in the bit lines of the conventional SRAM is lost to ground in each write operation during ‘1’ to ‘0’ transition and this is the main source of energy loss. The power dissipated in bit lines represents about 60% of the total dynamic power consumption during a write operation. The power consumption by bit lines during writing is proportional to the bit line capacitance, square of the bit line voltage and the frequency of writing. Energy loss is reduced by limiting voltage differences across conducting devices. This is accomplished through the use of time-varying voltage waveforms. This is also called Adiabatic charging technique. The SRAM working purely on adiabatic charging principles need multiple phase power clocks. Although there is huge saving in energy during writing as well as reading, the design of the SRAM circuit is complex and not same as the design of conventional SRAM. The latency of operation is more. No separate pre charging circuit is used before or after reading. No synchronization circuit is needed as only bit lines are concerned. Low power sense amplifier is utilized to sense the data. The design of the conventional SRAM can be retained except the write driver and the pre charge circuit. With this adiabatic driver circuit working in conjunction with conventional 6T SRAM cell other performance characteristics like read stability, write ability, read and write delay etc., have been found by simulation in addition to energy saving under varied conditions of memory operations. The effect of device parameters of the driver on total energy of the SRAM cell has been investigated. Further studies covered proposed SRAM cell arrays. In addition to recovering the energy from both bit lines the possibility of operating the SRAM cell with single bit line driven by an adiabatic driver is examined to save energy. This effort has resulted in realizing adiabatic 5T SRAM cell which consumes significantly lower energy than adiabatic 6TSRAM cell with reduction in bit line leakage power and with better Static Noise Margin (SNM).Single ended reading is employed and this does not need pre charging, which saves energy. Further the design of adiabatic 5T SRAM is modified to get Feat SRAM which has better speed of operation in addition to other performance parameters remaining almost the same. All these investigations have been carried out using CADENCE tool with 90nm. The thesis deals with the description of the effort put in to arrive at energy efficient adiabatic 6T and 5TSRAM cells whose other performance characteristics are almost comparable to those of 6Tconventional SRAM cell.