IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 2, FEBRUARY 2003 471 Development of High-Current 4H–SiC ACCUFET Ranbir Singh, Member, IEEE, D. Craig Capell, Mrinal K. Das, Lori A. Lipkin, and John W. Palmour, Member, IEEE Abstract—Planar 4H–SiC accumulation channel field effect transistor (ACCUFET) have been designed, fabricated, and characterized. Detailed design and processing experiments were conducted on relatively large area ACCUFETs to boost their power ratings. A detailed two-dimensional (2-D) simulation design suggests that the optimum spacing between two adjacent p regions is approximately 4 m. A novel process with epitaxial regrowth over ion implanted p base region was developed to achieve a high accumulation layer mobility. Process splits from nitrogen-rich post gate oxidation anneals revealed that the lowest on-resistance and optimum threshold voltage were obtained from N O annealed samples. 550 V blocking voltage with 22 m -cm were demonstrated on 2 A 4H–SiC ACCUFETs. Using a newly developed hex-gate design, larger, 20 A 4H–SiC ACCUFETs are presented here with stable high temperature characteristics. In these high-current devices, the threshold voltage decreases linearly from 1.5 V to 0.9 V, while the extracted channel mobility increases from 18 cm /V-s to 33.6 cm /V-s as the operating temperature is increased from 30 C to 200 C. Index Terms—Accumulation layer, FET, high temperature, MOSFET, power, switch. I. INTRODUCTION P OWER devices made with silicon carbide (SiC) are ex- pected to show great performance advantages as compared to those made with other semiconductors [1]. This is primarily because SiC has an order of magnitude higher breakdown elec- tric field (2–4 10 V/cm) than conventional materials, and an electron mobility only 20% lower than silicon [2]. A high breakdown electric field allows the design of SiC power de- vices with thinner and higher doped voltage blocking layers. A higher doped blocking layer provides lower resistance de- vices in 4H–SiC because more majority carriers are present than for comparably rated majority carrier devices in Si. Of the nu- merous SiC polytypes, 4H–SiC shows the best potential for high power operation because the electron mobility in 4H–SiC is 11 higher bulk electron mobility as compared to 6H–SiC parallel to the -axis, with measured mobilities as high as 1050 cm /V-s [3]. Moreover, 4H–SiC exhibits very small anisotropy in mo- bility making it attractive for the fabrication of vertical power devices. A large bandgap of SiC is also expected to result in a much higher operating temperature and higher radiation hard- ness. The requirement that a power device must be able to dis- sipate a significant amount of heat indicates that the thermal characteristics of the semiconductor are also of fundamental im- portance. The high thermal conductivity of 4.9 W/ C-cm in SiC Manuscript received August 19, 2002; revised November 4, 2002. This work was supported by the U.S. Air Force’s Wright Labs under Contract F33615-98-C-2843, monitored by C. Severt. The review of this paper was arranged by Editor M. A. Shibib. The authors are with Cree, Inc., Durham NC 27703 USA (e-mail: ranbir@ieee.com). Digital Object Identifier 10.1109/TED.2002.808511 allows heat generated to be readily extracted from a device, cor- respondingly increasing the power to be applied to the device for a given junction temperature. The ideal switch for most commercial applications is a high voltage, low on-state voltage drop MOSFET, because it offers ease of control of the power flowing through the device. In silicon, a double-diffused MOSFET (DMOSFET) is the most common structure used for fabricating power MOSFETs. Power MOSFET structures demonstrated in SiC include trench gate MOSFETs (called UMOSFETs here) [4], lateral MOSFETs [5] and planar double implanted MOSFET (DIMOSFETs) [6], [7]. Each of these has specific strengths and weaknesses. Since it is difficult to diffuse impurities in SiC, an inversion-mode UMOSFET offers a simple way to fabricate a MOSFET. A major problem in the UMOS structure is breakdown of the gate oxide at the bottom of the trench and the trench corners when the device is in the blocking state. This is because the electric field in the oxide is 2.5 that in the SiC in accordance with Gauss’ law, corresponding to the ratio of their dielectric constants. This problem is further exacerbated at trench corners leading to catastrophic failure of gate oxides at high temperatures and high voltages [8]. Lateral power MOSFETs in 4H–SiC are expected to suffer from high on-resistance unless very fine line lithography is used for their fabrication. Another important limitation in the performance of most inversion mode MOSFETs in 4H–SiC is the relatively low inversion channel mobilities. An accumulation-mode version of a UMOSFET has also been proposed utilizing a thin epitaxially grown n layer over the etched trench [9], [10]. This alleviates the problem of low channel mobilities, but suffers from oxide breakdown at trench corners. The DIMOS/DMOS structure offers high reliability, ease of integration with ICs and simplicity of fabrication because the gate oxide is shielded from the high electric fields by the adja- cent p-type base regions. The reason a DMOS structure is not typically considered for SiC MOSFETs is the extreme temper- atures required for obtaining significant dopant diffusion in SiC [7]. A DMOS device also requires a double diffused process, which requires a very good control over the implantation and diffusion process. Although much progress has been made in this aspect of SiC processing, it still has not reached a level of maturity that would promise a reliable, controllable and repeat- able process. Although high lateral inversion electron and hole mobilities of 72 and 25 cm /V-s have been achieved on 6H–SiC [11], the maximum lateral mobility achieved on 4H–SiC has been rather limited. While a 6H–SiC DMOS/DIMOS offers a low channel resistance, it suffers from a high drift region resis- tance. On the other hand, a 4H–SiC DMOS/DIMOS presently suffers from a high inversion channel resistance but offers a low drift region resistance. 0018-9383/03$17.00 © 2003 IEEE