Electron transport modeling in the inversion layers of 4H and 6H–SiC MOSFETs on implanted regions Yu Anne Zeng a, * , Marvin H. White a , Mrinal K. Das b a Sherman Fairchild Center/ECE Department, 16A Memorial Drive East, Lehigh University, Bethlehem, PA 18015, USA b Cree, Inc., 4600 Silicon Dr., Durham, NC 27703, USA Received 20 November 2004; received in revised form 25 February 2005; accepted 5 March 2005 Available online 21 April 2005 The review of this paper was arranged by Prof. A. Zaslavsky Abstract In this work, we present the characterization of electron transport in 4H and 6H–SiC inversion layers with the development of a physics-based, 2-D quantum-mechanical model to explain the I DS –V GS , g m –V GS device electrical characteristics, the field-effect and conductivity mobility behaviors. The model considers the combined effects of surface roughness and Coulomb scattering centers arising from fixed oxide charge and interface trapped charge. The experimental characteristics in 6H and 4H–SiC MOSFETs, fab- ricated on implanted regions, are presented and interpreted with this model. The peak field-effect mobility values for the 4H and 6H– SiC MOSFETs are 45 and 50 cm 2 V 1 s 1 , respectively. The peak conductivity mobility for the 4H–SiC MOSFETs are 37 before and 220 cm 2 V 1 s 1 after correction for interface trapped charge. The I DS –V GS , g m –V GS , and the field-effect mobility are modeled to an accuracy of 3% in subthreshold and strong inversion regions. Ó 2005 Elsevier Ltd. All rights reserved. Keywords: Quantum-mechanical; Mobility; Inversion; SiC; MOSFETs 1. Introduction As silicon-based devices reach their theoretical limita- tions for high-power and high temperature applications, silicon carbide (SiC) has emerged as a promising semi- conductor material to overcome these limitations be- cause of its high electric breakdown field (2.4 MV/cm), high electron saturation velocity (2 · 10 7 cm/s), and high thermal conductivity (3.0–3.8 W/cm °K). In addition, a native oxide can be thermally grown on SiC, which makes SiC very attractive for MOSFET fabrication. Various types of SiC power MOSFETs, such as UMOS [1,2] and DiMOS [3–5], have been demonstrated. How- ever, there are still many challenges associated with the development of practical SiC power MOSFETs. A high surface disorder called ‘‘step-bunching’’ [9] and a large interface trap density near the conduction band edge has been observed at the Si/SiO 2 interface [10,11]. The electron mobility in the inversion layer of SiC MOS de- vices has suffered from these interface disorders and dis- plays a much lower value than the bulk mobility [12]. Since the interface trapped charge is a strong function of the surface potential, the notion of a constant thresh- old voltage is no longer valid for SiC MOSFETs with high interface trap densities. Conventional silicon MOS theories, which assume a negligible interface trap density and a constant threshold voltage, have failed to explain the carrier transport in these devices where surface roughness is not the only issue but Coulomb scattering, arising from fixed oxide charge and inter- faced trapped charges, plays an important role as well. 0038-1101/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2005.03.002 * Corresponding author. Tel.: +1 2083635218; fax: +1 2083682548. E-mail address: annezenglehigh@yahoo.com (Y.A. Zeng). www.elsevier.com/locate/sse Solid-State Electronics 49 (2005) 1017–1028