International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1473 Switch Level Implementation of a 4-Bit Logical Unit using Mixed Logic Design Method Binita Susan John 1 , Tintu Mary John 2 1 PG Scholar, Dept. of ECE, Believers Church Caarmel Engineering College, Kerala-689711, India 2 Asst.Professor, Dept. Of ECE, Believers Church Caarmel Engineering College, Kerala-689711, India ---------------------------------------------------------------------***---------------------------------------------------------------------- Abstract – This paper introduces a logical unit by means of low power gates which is executed by switch level modeling. The ALU entails of a logical unit and arithmetic unit. The logical unit performs operations such as decision making etc. The low power structure of the two-to-four decoder is modified and prolonged to form four bit logical unit to implement AND,OR,XOR,XNOR operations. Finally the simulations are carried out by switch level modeling. The layout of the logical unit was acquired by Microwind 2 design layout software. Key Words: ALU, Mixed-logic, switch level modeling, Low power gates, transmission gates 1. INTRODUCTION An ALU is the figuring and basic leadership hardware of any chip or microcontroller. ALUs of different piece widths are frequently required in extensive scale incorporated circuits (VLSI) from processors to application explicit coordinated circuits (ASICs). ALU is getting littler and progressively complex these days to empower the advancement of an increasingly prevailing however littler PC. The ALU consists of arithmetic and logical unit. The logical unit accomplishes various operations which are used for decision making, error detection, error correction, generating combinational functions. The 74181 is a distinctive four-bit ALU, commercially reachable as an integrated circuit chip. This IC is built using TTL technology. It performs arithmetic operations, bit manipulations, and logical operations. Few of its logical operations are the four bit AND, OR, XOR, and XNOR. Pass transistor was mostly settled in 1990s and few plan styles were explained [3-6].A logical unit can be implemented using a variety of technologies. Different methodologies are utilized for the logical unit implementation such as reversible gates, for example GDI- approach; pass transistor logic etc. D. Balobas and N. Konofaos in [1] present a new technique for the line decoders. They consolidated transmission gates, dual value logic and static CMOS and obtain four new designs and comparison has been done. For then simulation process all the circuits designed were simulated at 3 diverse operational frequencies and 3 distinctive supply voltages with various temperatures. The comparison results demonstrates that there is 7.4%, 6.5% and 6.0% lower power, 4.5%, 9.3% and 2.3% lower delay and 11.1%, 15.3% and 7.9% lower PDP, individually. Reto Zimmermann and Wolfgang fichter in [2] conducts a logic style comparison which was based on full adder circuits. They found from the results that complementary CMOS can be used for the execution of arbitrary combinational if low voltage , low power and small power delay are taken into account. Suzuki, et al. in [4] introduces 1.5 ns 32b CMOS ALU which is fabricated at 0.25µm CMOS technology and 2.5V supply. They utilized double pass transistor logic and carry ahead adder circuit for the expansion time. This proposed paper consists of two parts. Firstly, the functional simulation and verification of all the structures proposed in [1].Secondly, the implementation of a four-bit logical unit using mixed-logic designs method. The functional simulation and verification of all these structures were carried out by switch level modeling, using Verilog HDL.The functional verification of the LP, LPI, HP and the HPI structures of the two-to-four and four-to-sixteen decoders were carried out. The input-output vector pairs of the functional simulation were verified and found to be precise. Further, the LP structure of the two-to-four decoder is improved and is extended to form a four-bit logical unit to execute AND, OR, XOR and XNOR operations. The LP structure of the 4-bit logical unit was instigated using 198 transistors. The rest of the paper is organized as follows: Section 2 gives a brief overview on the existing including low power gates, mixed logic design method. Section 3 provides an explanation about the proposed system using low power gates. Section 4 provides simulation results of the four bit logical unit. Section 5 provides the conclusion of the work presented. 2. EXISTING SYSTEM An innovative mixed-logic design method involving TGL, DVL, and static CMOS was proposed in [1] to build four structures of two-to-four decoder. These structures are the low power (LP and LPI) and the high performance (HP and HPI) which are simulated by them using BSIM 4- based SPICE software at schematic level with 32 nm technology. To compare the performances of the mixed-logic method, they constructed a two-to-four decoder. At first, they designed a low power (LP) and low power inverting (LPI) structure, using fourteen transistors. Moreover, they designed a high performance (HP) and high performance inverting (HPI) structure using