Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs Luca Benini (1) , Davide Bertozzi (2) , Alessio Guerri (1) , and Michela Milano (1) (1) DEIS, University of Bologna V.le Risorgimento 2, 40136, Bologna, Italy {lbenini, aguerri, mmilano}@deis.unibo.it (2) Dipartimento di Ingegneria, University of Ferrara V. Saragat 1, 41100, Ferrara, Italy dbertozzi@ing.unife.it Abstract. In this paper we introduce a complex allocation and schedul- ing problem for variable voltage Multi-Processor System-on-Chip (MP- SoC) platforms. We propose a methodology to formulate and solve to optimality the allocation, scheduling and discrete voltage selection prob- lem, minimizing the system energy dissipation and the overhead for fre- quency switching. Our approach is based on the Logic Benders decom- position technique where the allocation is solved through an Integer Pro- gramming solver, and the scheduling through a Constraint Programming solver. The two solvers are interleaved and their interaction regulated by cutting plane generation. The objective function depends on both master and sub-problem variables. We demonstrate the efficiency of our approach on a set of realistic instances. 1 Introduction As silicon technology keeps scaling, it is becoming technically feasible to inte- grate entire and complex systems on the same silicon die. This solution provides scalable computation power, and it is expected that hundreds of processor cores will be integrated on these Multi-Processor Systems-on-Chip (MPSoCs) in fu- ture technologies. MPSoCs are widely used in embedded systems (such as cellular phones, automotive control engines, etc.) where, once deployed in field, they al- ways run the same set of applications. Since for many multimedia and signal processing applications the workload is highly predictable at design time, with minimum run-time fluctuations, an optimal allocation and scheduling for such applications can be statically derived off-line. A critical task for recent MPSoCs is the minimization of the energy consumed since the speed of each processor can be tuned by changing its frequency. We start from a well-characterized task graph, a directed acyclic graph representing a functional abstraction of the application that will run on the MPSoCs. Each task is characterized by the number of clock cycles used for its execution. Clearly the duration of each task and the energy spent for running it depends on the