ARTICLE IN PRESS JID: NEUCOM [m5G;August 1, 2019;18:49] Neurocomputing xxx (xxxx) xxx Contents lists available at ScienceDirect Neurocomputing journal homepage: www.elsevier.com/locate/neucom IEEE 754 floating-point addition for neuromorphic architecture Arun M. George a , Rahul Sharma b,∗ , Shrisha Rao c a TCS Research and Innovation, Bangalore, India b Continental Automotive Components India Pvt Ltd, Bangalore, India c International Institute of Information Technology-Bangalore, Bangalore, India a r t i c l e i n f o Article history: Received 6 July 2018 Revised 27 January 2019 Accepted 16 May 2019 Available online xxx Communicated by Dr Chenchen Liu Keywords: Neuromorphic computing Neuromorphic architecture Floating-point arithmetic IEEE 754 Nengo Neural engineering framework a b s t r a c t Neuromorphic computing is looked at as one of the promising alternatives to the traditional von Neu- mann architecture. In this paper, we consider the problem of doing arithmetic on neuromorphic systems and propose an architecture for doing IEEE 754 compliant addition on a neuromorphic system. A novel encoding scheme is also proposed for reducing the inter-neural ensemble error. The complex task of float- ing point addition is divided into sub-tasks such as exponent alignment, mantissa addition and overflow- underflow handling. We use a cascaded approach to add the two mantissas of the given floating-point numbers and then apply our encoding scheme to reduce the error produced in this approach. Overflow and underflow are handled by approximating on XOR logic. Implementation of sub-components like right shifter and multiplexer are also specified. © 2019 Elsevier B.V. All rights reserved. 1. Introduction Neuromorphic computing has emerged in recent years as a plausible future alternative to the pervasive and long-standing von Neumann architecture. The term “neuromorphic computing” was coined by Mead [1], who referred to Very Large Scale Integration (VLSI) systems with analog components that mimicked biologi- cal neural systems. These neuromorphic architectures are known for their high parallelism and low power needs. Neuromorphic ar- chitectures have also received increased attention because of the approaching end of Moore’s law [2] and the bandwidth restric- tions between CPU and memory known as “the von Neumann bot- tleneck” [3]. With energy efficiency being crucial for future high performance and embedded computing platforms, neuromorphic computing offers a solution to today’s rising demands in comput- ing [4]. Neuromorphic computing is not yet a practical technology in a mainstream sense (see the tutorial by Volanis et al. [5] and the survey by James et al. [6]), but there are efforts to make it work using classical VLSI technologies [7,8]. One issue that is currently being addressed is energy efficiency [4,9,10]. Newer technolo- gies, particularly memristors [11,12] are also being considered as possible routes for implementing neuromorphic architectures. ∗ Corresponding author. E-mail addresses: arun.george@iiitb.org (A.M. George), rahul.sharma112@iiitb.org (R. Sharma), shrao@ieee.org (S. Rao). Neuromorphic computing is also studied by neuroscientists who wish to model or understand the brain [13–15], and by those who wish to mimic the functionality of sense organs [16]. Machine learning also provides another important reason for interest in neuromorphic computing [8,17,18]. Recent years have seen several breakthroughs in neuromorphic hardware which address some important concerns with the uses of the same (such as the lack of accuracy), and also expand the range of applications possible with neuromorphic computing. Interest- ing new hardware avenues include the neuromorphic processors Loihi [19] and Braindrop [20]; the use of non-volatile memory [21], on-chip communication [22] and reconfigurability through hierar- chical addressing [23]; and the DYNAPs architecture [24]. New pro- posed uses of neuromorphic computing include network applica- tions [25] and matrix-vector multiplication [26]. Floating-point arithmetic is crucial for most scientific com- puting. Any new computing architecture, therefore, would need a system that can perform floating-point arithmetic. In this paper, we propose a system which can perform the addition of two IEEE 754-compliant floating-point numbers on a neuromorphic architecture. We have designed a system which follows the con- ventional addition process [27] but works on groups of neurons in- stead of logic gates. There have been previous attempts to develop systems of computation on neuromorphic architectures [6,28] but not much has been done in the area of numerical computations, especially in the area of floating-point arithmetic. The novelty and significance of our work is to explore this area to understand how https://doi.org/10.1016/j.neucom.2019.05.093 0925-2312/© 2019 Elsevier B.V. All rights reserved. Please cite this article as: A.M. George, R. Sharma and S. Rao, IEEE 754 floating-point addition for neuromorphic architecture, Neurocom- puting, https://doi.org/10.1016/j.neucom.2019.05.093