IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 52, NO. 10, OCTOBER 2006 4519 A Necessary and Sufficient Condition for the Construction of 2-to-1 Optical FIFO Multiplexers by a Single Crossbar Switch and Fiber Delay Lines Chih-Chieh Chou, Member, IEEE, Cheng-Shang Chang, Fellow, IEEE, Duan-Shin Lee, Senior Member, IEEE, and Jay Cheng, Member, IEEE Abstract—In this paper, we prove a necessary and suffi- cient condition for the construction of 2-to-1 optical buffered first-in–first-out (FIFO) multiplexers by a single crossbar switch and fiber delay lines. We consider a feedback system consisting of an crossbar switch and fiber delay lines with delays . These fiber delay lines are connected from outputs of the crossbar switch back to inputs of the switch, leaving two inputs (respectively, two outputs) of the switch for the two inputs (respectively, two outputs) of the 2-to-1 multi- plexer. The main contribution of this paper is the formal proof that and , , is a necessary and sufficient condition on the delays for such a feedback system to be operated as a 2-to-1 FIFO multiplexer with buffer under a simple packet routing policy. Specifically, the routing of a packet is according to a specific decomposition of the packet delay, called the -transform in this paper. Our result shows that under such a feedback architecture a 2-to-1 FIFO multiplexer can be constructed with , where is the buffer size. Therefore, our construction improves on a more complicated construction recently proposed by Sarwate and Anantharam that requires under the same feedback architecture (we note that their design is more general and works for priority queues). Index Terms—Exact emulation, first-in–first-out (FIFO) queues, optical multiplexers, switched delay lines. I. INTRODUCTION T O build high-speed packet switches that scale with the speed of fiber optics, one needs to resolve conflicts of packets that compete for the same resources. Traditionally, such conflicts are resolved by first converting optical packets into electronic packets, storing them in electronic buffers, and then converting electronic packets back into optical packets. However, such an approach incurs tremendous overheads in both the O-E conversion and the E-O conversion. Considering that all-optical switches and signal processing have been successfully demonstrated recently [1], the design of optical Manuscript received November 7, 2005; revised April 20, 2006. This re- search was supported in part by the National Science Council, Taiwan, R.O.C., under Contract NSC-93-2213-E-007-040, Contract NSC-93-2213-E-007-095, Contract NSC-94-2213-E-007-046, and the Program for Promoting Academic Excellence of Universities NSC –94-2752-E-007-002-PAE. The authors are with the Institute of Communications Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan, R.O.C (e-mail: u880913@alumni.nthu.edu.tw; cschang@ee.nthu.edu.tw; lds@cs.nthu.edu.tw; jcheng@ee.nthu.edu.tw). Communicated by E. Modiano, Associated Editor for Communication Net- works. Digital Object Identifier 10.1109/TIT.2006.881712 buffers has become one of the most critically sought after optical technologies in all-optical packet-switched networks. Recent advances in optical technologies have made feasible the constructions of compact and tunable optical buffers by using the so-called “slow light” technique [2]–[6]. Therefore, the construction of an optical buffer may not be as bulky as one might expect as it can now be implemented in the nanoscale [2]. Also, the synchronization issue that is usually of practical concern may not be a critical design obstacle as it has been demonstrated that a 75-ps pulse can be delayed by up to 47 ps [6]. As such, constructing optical buffers directly via optical Switches and fiber Delay Lines (SDL) has been recognized as one of the promising technologies for the design of optical buffers, and there has been recent intensive research interest in this regard. The idea of using SDL for buffering is to distribute optical packets (by optical switches) over fiber delay lines with various lengths so that packets competing for the same resources can be resolved. Early works in this direction include the CORD (COntention Resolution by Delay lines) project [7]–[9] and the feedback system by Karol [10]. Those early works mainly fo- cused on the feasibility of SDL, not on the theoretical aspect of SDL. In particular, the feedback system in [10] was proposed for approximating a shared buffered switch. In [11] and [12], a genuine SDL design, named COD (Cas- caded Optical Delay-lines), was proposed for exact emulation of 2-to-1 buffered first-in–first-out (FIFO) multiplexers by using crossbar switches and fiber delay lines. Though it is easy to control the switches in COD, the cost in terms of the number of switches in COD is linear in the buffer size. In [13], a more efficient design, called Logarithm Delay-Line Switch, was proposed for 2-to-1 buffered FIFO multiplexers. The number of switches needed for such an architecture is only , where is the buffer size. More recently, it was shown in [14] that there is a recursive method for constructing a larger 2-to-1 buffered FIFO multiplexer by connecting smaller 2-to-1 buffered FIFO multiplexers. The construction in [13] is a direct result of the recursive expansion in [14]. For other related works in SDL, we refer to [15]–[19] and the references therein. All the above works on 2-to-1 buffered FIFO multiplexers are based on multistage construction of SDL elements. Recently, Sarwate and Anantharam [20] considered a feedback architec- ture as in [10] that is comprised of an crossbar switch and fiber delay lines with delays , and proposed a construction for exact emulation of priority queues, 0018-9448/$20.00 © 2006 IEEE