International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 7737 DESIGN OF MEMRISTOR BASED MULTIPLIER Neha Jagan, Raksha S, Namitha S U, Shafiya Kouser 1 , Ms.B.S sharmila 2 1 Final year B.E under graduates, The National Institute of Engineering, Karnataka, India 2 Assistant Professor, Department of ECE, The National Institute of Engineering,Karnataka, India ---------------------------------------------------------------------***---------------------------------------------------------------------- Abstract - Memristor is a novel technology, the fourth fundamental passive element to overcome the limitations faced by the CMOS technology. Memristor has the capacity of memory but cannot store energy[9]. Multiplier is one of the basic circuits in the field of digital signal processing and are used in various applications such as FFT. In this paper, a 4 bit multiplier is realised and implemented using the memristor- cmos hybrid technology and the results are analysed in the LTspice tool. Key Words: Memristor, window function, state variable, array multiplier, xnor, full adder. 1. INTRODUCTION In 1971,Professor Leon Chua discovered the existence of the fourth fundamental passive element known as the memristor. But its research had not progressed untill 2008 because of the absence of physical prototype of the memristor. With the invention of physical modelling of memristor device in 2008 by the HP Labs, there has been a drastic increase in the research to realise various existing circuits in memristors. Multiplication is one of the key operation in digital signal processing algorithms like digital filtering, linear transformation, correlation and wavelet compression.Various effiicient array and parallel multipliers have been proposed and many of them boost the speed of multiplication at the cost of large VLSI area and high power dissipation[1]. In recent years, several power reduction techniques have been proposed for low power digital design, including the reduction ofsupply voltage, multi-threshold logic and the clock speed, the use of signed magnitude arithmetic and differential data encoding,the parallisation of operations and the timing if input bit patterns to reduce switching[2]. A basic multiplier can be divide into 3 parts 1).partial product generation 2).partial product addition and 3).final addition. It has been recognised that full adder circuits have significant impact on the overall power and area consumption and the speed of multipliers built on these adders. Many new full adder circuits have been proposed and here,xnor based full adder is implemented in array multiplier which can be extended to other multipliers and studied. In this paper, we implemnt an area efficient array multiplier that uses memristor-cmos hybrid technology. The rest of the paper is organised as follows.section II consists of brief description of memristor working. Section III explains the concept of window functions for memristor and the various window functions experimented in this project and its outcome. Section IV implements the 2 bit and 4 bit array multiplier structure with the memristor-cmos hybrid technology.The results are analysed analysed in LTspice tool in section V. section VI presents the conclusion of the work. 2. MEMRISTOR WORKING In 2008, the HP laboratory team developed the memristor element with typical resistive features successfully. The range of memristor value reflects the memory effect and is equal to the time integration of the currents that cross through the memristor before the time instant[6]. Memristor reflects the relationship between the charge and the magnetic flux, and accordingly to these fundamental circuit variables, a memristor can be divided into two types, the charge controlled memristor and the flux controlled memristor[6]. The titanium-dioxide memristor nano-structure is described by Strukov and William as in figure 1.The left region if the TiO2 memristor structure with a length l is partially doped with process with oxygen vacancies using an initial electroforming process with a high constant voltage and has low resistance[8]. The second sub-layer of the memristor is prepared of pure TiO2 and it has very high resistance. The length of the whole memristor nano-structure is denoted with D [8]. Fig-1: memristor nano structure The equivalent resistance of the memristor element could be expressed as assumption of series connection of doped and undoped regions[8] as given in figure 2. R=Rdoped + Rundoped