Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee Research paper A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications N. Paras ⁎ , S.S. Chauhan Department of Electronics and Communication Engineering, National Institute of Technology, Kuruskshetra, India ARTICLE INFO Keywords: Hetero-gate SS TFET Vertical tunneling ABSTRACT In this paper, we propose a novel germanium source based dual metal gate tunneling feld efect transistor (VGeDMG). Design of device efectively suppresses lateral tunneling current component and facilitates dom- inance of vertical tunneling components which results in a substantially improved subthreshold slope. The dual gate in the design of the device gives the fexibility to control and improve the ON-current, OFF current and threshold voltage of the device signifcantly. In addition to the digital fgure of merits, analog and RF perfor- mance of the proposed device is calculated and comparison with silicon source dual metal gate (conventional) TFET (SiDMG) and silicon source dual metal gate vertical TFET (VSiDMG) shows that the proposed device outperformed both the devices. The design fulflls the high-performance ON-state current of 1.20 mA, low standby power OFF-state current nearly of 3.63 fA, and SS 26 mV/decade indicating that the proposed TFET follows the ITRS roadmap for low standby power switch performance. 1. Introduction Conventional MOSFETs have been scaled down continuously for improving the current driving capability, cost savings, increasing the device density, improved RF performance [1–2]. But, rigorous minia- turization below 32 nm has deteriorated the device performance [3] and MOSFETs are unable to fulfll the present low-power applications requirements because of their non-scalable SS behavior at 300 K. In this regard, TFETs has been observed as suitable alternatives to conven- tional MOSFET. Instead of using the classical mechanism of thermionic emission, quantum tunneling mechanism based band to band tunneling (BTBT) of charge carries occurs in TFETs thus overcoming the short- comings of MOSFETs [4–6]. Because of low drive current of conven- tional silicon p-i-n TFETs, they are unacceptable for low-power appli- cations [7–8]. For improving the ON state current of TFETs, various schemes were proposed such as double gate TFET, hetero-dielectric buried oxide, silicon on insulator (SOI) substrate based TFET with raised buried oxide in the drain has been studied in [9–13], which shows increased ON current, transconductance (g m ) as well as mini- mized OFF current. Later on, SCEs reduction has been investigated in [14] by studying analytical structure of double gate structures. Further, junctionless TFET [15–18] with higher doping concentration (> 10 17 atoms/cm 3 ) is examined by the researchers but these devices face several challenges such as low drive current due to large source/drain resistance and high work-function on metal electrodes is required to turn of the device [19]. Gate to drain capacitance gets increased and poses problem of scalability in case of structures having gate/drain overlap design [20]. Gaussian doping in drain region [21] for mini- mizing ambipolar behaviour is not feasible for dopingless devices [22] and fabrication is not possible in case of nano scale physically doped devices with existing technology. So far, TFETs continue to sufer from an imminent issue of simultaneous optimization of SS and I ON /I OFF which has not been achieved yet due to the difculty in suppressing the OFF current or the lateral tunneling component. For this purpose, a vertical tunneling based Ge-source dual metal gate TFET (VGeDMG) with high k gate dielectric material is introduced in this paper. In the proposed device, gate overlaps the source region with a thin silicon channel sandwiched between the gate oxide and source. This result in suppression of lateral tunneling component and high vertical tunneling current density and band to band generation rate is achieved. This results in steep SS and high I ON /I OFF ratio. Further, two diferent workfunction metals are placed on the gate electrode on source and drain side namely the Tunnel Gate (TG) and the Auxiliary Gate (AG) respectively. The tunnel gate modulates the energy https://doi.org/10.1016/j.mee.2019.111103 Received 7 April 2019; Received in revised form 29 July 2019; Accepted 2 August 2019 ⁎ Corresponding author. E-mail addresses: neharao1993@gmail.com (N. Paras), sudakar@nitkkr.ac.in (S.S. Chauhan). Microelectronic Engineering 217 (2019) 111103 Available online 03 August 2019 0167-9317/ © 2019 Elsevier B.V. All rights reserved. T