2016 International Conference on Control, Computing, Communication and Materials (ICCCCM) 978-1-4673-9084-2/16/$31.00 ©2016 IEEE Short channel effects (SCEs) characterization of underlaped dual-K spacer in dual-metal gate FinFET device Lucky Agarwal, Brijesh Kumar Singh, R. A. Mishra and Shweta Tripathi Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad Abstract— FinFETs are new structures for scaling the devices at sub-nanometer regime to continue the Moore’s law. To increase the performance of FinFETs, a dual metal gate with underlap concepts has been introduced. Moreover, its performance can be enhanced by spacers. The dual metal gate comprises of two different workfunction materials (Molybdenum and Tungsten) for double gate (DG) and triple gate (TG) FinFET structures with different underlap length (L UN ) has been presented. The TG FinFET exhibits the better control of short channel effects (SCEs) over the DG FinFET device. The significance of the spacer with a variation of spacer length poses the use of dual-k spacer in TG FinFET device to procure the better performance such as high on-current (I on ), I on/ I off ratio and smaller subthreshold swing (SS), drain induced barrier lowering (DIBL). The simulation carried by SILVACO ATLAS, and it shows that TG FinFET with different combination of dual-k (smaller high-k length (L hk ), larger low-k length (L lk )) draws an attention for nanoscale application. Index Terms— Dual Metal Gate FinFET, Fringing field effect, High-k spacer, Low-k spacer, Short channel Effects (SCEs) Underlap/non-underlap channel. I. INTRODUCTION As the technology is expanding in the field of semiconductor MOSFET devices are continuously being scaled down due to which controlling activity of gate over the device channel is a discrepancy from its performances hence, several undesirable effects such as SCEs emerges out whose control is of major concern nowadays. SCEs reduce the electrostatic integrity [1]. Nonscalability property of subthreshold swing and increment in threshold voltage (V T ) puts a limit on shrinking the dimension of MOSFET in nanometer regime [2]-[3]. The silicon on insulator (SOI) based transistor emerges out as one of the most promising technology to shrink the dimension of a transistor upto 100nm range which improves the driving current capability of the transistor [4]-[6], but still SCEs does not completely eliminate. In order to reduce the random dopant fluctuation, channel is lightly doped [7], so that the mobility of the carriers increases due to reduction of body scattering effect. MOSFET with double or triple gate (DG FinFET, TG FinFET) have been assembled in order to enhance device imension shrinking capability & suppress SCEs in comparison of standard bulk MOSFET [8-10]. Threshold voltage of a FinFET depends on the work function of metal which is a major concern for lightly doped channel [11]. Reduction of threshold voltage to increase current derive brings the concept of the dual metal gate. Here in this paper used metal with work function are aluminum (Φ F =4.1) tungsten (Φ F =4.63), molybdenum (Φ F =4.81). SS can be improved by using spacer which suppresses SCEs due to electrically induced extension region [12]. Making underlap region lightly doped lead to reduction in leakage current but I on degrades due to enhancement in source/drain resistance (R S/D ) [13]. The concept of using high-k spacer is required due to a trade-off between R S/D (source/drain resistance) and fringe field [14]. Short channel devices due to the inefficiently scaled spacer width suffer from the fringing field effect [15] therefore in this paper effect of fringing field and series R S/D is analyzed by a comparative study of non- underlap/underlap channel, single-k spacer of different dielectric at different position along underlap, and lastly with dual-k spacer of variable length in TG FinFET structure is done and result is optimized for Subthreshold swing (SS) (is the required change in gate-source voltage to change the drain current 10 times in the subthreshold region of the device), DIBL(drain induced barrier lowering i.e. change in threshold voltage with respect to change in gate to source voltage) and leakage current (flows in a device when no power supply is given to device due to diffusion of carriers). This paper is divided into 4 Sections. Section II describes the device structure simulation part and study of underlap and non-underlap is done with different dielectric material, such as SiO 2 (k=3.9), Si 3 N 4 (k=7.5), Al 2 O 3 (k=11.5), HfO 2 (k=25). Section III comprises a study and a comparison report of a single-k spacer in underlap region of variable length with fixed underlap length is discussed. Section IV incorporates proposed device i.e. dual metal gate with dual-k spacer which is analyzed for different combination of spacer at different length. Results are compared and optimized. The paper is summarized in section V. Channel Drain Source L UN M1 M2 M1 M2 Fig. 1 Top view of TG FinFET