Design of a High Speed, Low Power, Static Phase Error Free Phase Frequency Detector using Modified GDI NAND Logic Antardipan Pal 1 M.Tech, VLSI Design & Microelectronics Technology Department of Electronics & Telecommunication Engineering Jadavpur University Kolkata, India. Mail: ap1331@gmail.com Dr. Salil Kumar Sanyal 2 Professor Department Of Electronics & Telecommunication Engineering Jadavpur University Kolkata, India. Mail: salil_sanyal@etce.jdvu.ac.in Abstract: This paper proposes the design of a high speed and low power Phase Frequency Detector (PFD) with almost negligible static phase error or dead zone. It uses lesser number of MOSFETs as compared to traditional PFD designs using TSPC Logic. The proposed design uses the Modified GDI NAND Gates and is more energy efficient (has lesser power delay product) as compared to the CMOS counterpart. The abolition of logic gates in the reset path of the proposed circuit has minimized the dead zone appreciably. The proposed PFD circuit has been simulated using 65nm CMOS technology and a supply voltage of 1V. Key words: GDI, PFD, TSPC, Dead Zone I.INTRODUCTION Phase Frequency Detectors (PFDs) are one of the most crucial blocks of Phase Locked Loops (PLLs)[1] which form an integral part of Wireless Communication Systems. Phase Frequency Detector, as the name suggest compares the phase and Frequency of two signals and produces output voltage proportional to the phase or frequency difference between the two signals[2].PFDs are most popular form of phase detectors as opposed to Analog Multipliers[2] followed by Low Pass Filters and Digital PDs using Ex-OR Gates ,since they have larger lock in range, do not lock on the harmonics of the input data, have higher output frequency range and lock in time is independent on the input data pattern [2] .The performance of a PFD is much hindered due to the dead zone [3] which predominantly occurs when the input phase delay is small enough and comparable to the component delay of the PFD circuit. This paper presents a versatile technique to minimize the dead zone problem. Also with advancements in technology multifunctional Communicational devices have become very popular. This calls for higher circuit speed of operation along with low power consumption. Modified Gate Diffusion Input (GDI) technique [4] provides a good alternative to traditional CMOS designs for lower power and higher speed of operations. The PFD design proposed in this paper has minimum dead zone due to the abolition of logic gates from the reset path. Modified GDI NAND [5], [6]used in the proposed circuit reduces the power consumption and increase the speed of operation by appreciable amount .So overall a high speed and low power PFD is obtained as compared to other designs with traditional CMOS logic. Modified GDI technique is used as opposed to basic GDI technique since the former has lesser leakage power dissipation due to the connection of the substrates of the pMOS and nMOS to VDD and ground respectively. II.WORKING PRINCIPLE A PFD is a circuit that compares both the phase and frequency of the input reference signal and the feedback signal form the Voltage Control Oscillator(VCO) [2] .The block diagram of the PFD as shown in Fig.1 consist of 2 D Flip Flops and a AND Gate. The D inputs of both the Flip Flops are connected to the supply (Logic 1) and the 2 input signals are given to the clock input of the Flip Flops. When the rising edge of the reference input data leads the feedback dclock signal in time then the upper D Flip Flop is On and UP=1 while DOWN=0. When the rising edge of the dclock signal leads the data input then lower D Flip Flop is On and DOWN =1 while UP=0 .When the rising