International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 01 | Jan 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1031 An Efficient Multiply Accumulate Unit Design using Vedic Mathematics Algorithm Amandeep Kaur 1 , Balpreet Kaur 2 , Rupinder Kaur 3 1,2,3 Assistant Professor, Dept. of CSE, BBSBEC, Fatehgarh Sahib --------------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - A novel technique for digital multiplication is explained and used that is differs from conventional multiplication method using add and shift [4]. This is an implementation of modular design style where smaller blocks are used to design bigger blocks of NxN multiplier. Using this multiplier, a Multiply Accumulate Unit has been designed which shows less computation time for performing MAC operation. Key Words: Verilog, Digital Multiplier, Multiply Accumulate Unit 1. INTRODUCTION Multiply-accumulate operation is one of the basic arithmetic operations extensively used in modern digital signal processing (DSP). Operations such as digital filtering, convolution and fast Fourier transform (FFT), requires high-performance multiply accumulate operations. A Digital Multiplier is the heart of the MAC unit. The performance of MAC unit greatly depends on the multiplier [2]. This paper presents a systematic design for fast and efficient MAC unit using Vedic Mathematics [1]. This paper is organized into two sections. Section 1 presents the design methodology for NxN bit Vedic Multiplier and in Section 2, the design of Multiply Accumulate Unit, using Vedic Multiplier is explained. 2. Vedic Multiplier To design a NxN multiplier, we need a 2X2 multiplier as a building block.[3] Talking about 2X2 multiplier, lets take two inputs say A (a1,a0) &B(b1,b0) , each two bits wide and the result be S (s3,s2,s1,s0) which is 4 bits wide. During this multiplication, 4 partial products are generated due to vertical and crosswise multiplication which are a0b0, a0b1,a1b0 and a1b1. The partial product a0b0 directly passes on to the product S as s0, where as the LSB of sum of a0b1 and a1b0 forms s1. The carry bit is added to partial product a1b1 to determine s3 and s2 as MSB and LSB after addition respectively. 2 bit Multiplication by this method is shown in figure 1. Fig- 1: Block Diagram of 2 bit Multiplier Using the same technique as 2x2 bit vedic multiplier, 4,8,16 and 32 bit multipliers can be designed with slight modification. That is, the input bits need to be grouped into two halves of the input bit stream. Input bit steams ( of say N bits) can be divided into (N/2 = n) bit length, which can be further divided into n/2 bit streams and this can be continued till we reach bit streams of width 2, which can be multiplied in parallel, using 2x2 multiplier blocks[1]. Let us demonstrate this using a 4x4 multiplier which uses 4, 2x2 multipliers as its building blocks. Inputs A and B are assumed as 1101 and 1010 respectively which are grouped in chunks of 2 bits each and multiplied using 2x2 multipliers in parallel, as shown in figure.