Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems Jos´ e L. Ayala 1 , Anya Apavatjrut 2 , David Atienza 3,4 , Marisa L ´ opez-Vallejo 1 1 Departamento de Ingenier´ ıa Electr´ onica Universidad Polit´ ecnica de Madrid (Spain) Email: {jayala, marisa}@die.upm.es 2 Department of Telecommunication Services and Usage INSA (Lyon, France) Email: anya.apavatjrut@insa-lyon.fr 3 Departamento de Arquitectura de Computadores y Autom´ atica Universidad Complutense de Madrid (Spain) 4 LSI Ecole Polytechnique F´ ed´ erale de Lausanne (Switzerland) Email: david.atienza@epfl.ch Abstract This paper presents a thermal model to analyze the tem- perature evolution in the shared register files found on VLIW systems. The use of this model allows the analysis of several factors that have an strong impact on the heat transfer: layout topology, placement and memory accesses. Finally, some relevant conclusions are obtained after ana- lyzing the thermal behavior of several multimedia applica- tions. 1 Introduction As technology scales, higher power consumption cou- pled with smaller chip area will result in higher power den- sity, which in turn will lead to higher power temperature on the chip [1, 2]. In fact, extrapolating the changes in micro- processor organization and the device miniaturization, one can project future power density to 200W/cm 2 [3]. This requires extensive efforts on cooling techniques which have shown to be complex and expensive. While hardware solutions to temperature management problems are very important, software can also play an im- portant role because it determines the circuit components exercised during the execution and the period of time for which they are used. In particular, compilers and source code transformations determine the data and instruction ac- cess patterns of applications, what shapes the power density profile. Also, the topology of the hardware modules and the placement of these components determine the temperature behavior. In this paper we present a complete parameterized ther- mal characterization of one of the hardware modules that can be found in a VLIW architecture, the shared register file. The experimental approach analyzes the effect of the topology of this device, as well as the placement in the chip layout, in the temperature behavior if the chip when differ- ent applications are run. The contributions of this paper are: 1. Definition of a mathematical model to analyze the tem- perature behavior of the registers found inside the reg- ister file of a VLIW architecture. This model is inte- grated in a complete simulator of VLIW architectures in order to use the bus activities and register file ac- cesses as input parameters for the model. 2. Analysis of the effect on the temperature behavior of different register file topologies, module placements and register access pattern. 3. Characterization of several multimedia applications to evaluate the common characteristics in terms of tem- perature behavior. This paper is composed as follows: Section 2 presents the previous relevant works in this topic, while our pro- posed methodology and thermal model are briefly explained in Section 3. Also, some optimization policies are presented International Workshop on Innovative Architecture for Future generation Processors and Systems 2007 1527-1366/08 $25.00 © 2008 IEEE DOI 10.1109/IWIA.2007.7 81 International Workshop on Innovative Architecture for Future generation Processors and Systems 2007 1527-1366/07 $25.00 © 2007 IEEE DOI 10.1109/IWIA.2007.7 81