A semi-analytical approach for optimized design of microchannel liquid-cooled ICs * Arvind Sridhar, Mohamed M. Sabry, David Atienza École Polytechnique Fédérale de Lausanne (EPFL), Switzerland {arvind.sridhar, mohamed.sabry, david.atienza}@epfl.ch Abstract The development of embedded and interlayer liquid cooling in integrated circuits (ICs) using silicon microchannels has gained interest in the recent years owing to the rise of on-chip heat uses that aggravate thermal reliability issues of the emerging 3D stacked ICs. Further development of such devices and their translation to commercial applications depend largely on the availability of tools and methodologies that can enable the “temperature-aware” design of liquid- cooled microprocessors and 2D/3D multiprocessor systems-on-chip (MPSoCs). Re- cently, two optimal design methods have been proposed for liquid-cooled microchannel ICs: one to minimize on-chip tem- perature gradients and the other, called GreenCool, to max- imize energy efficiency in the coolant pumping effort. Both these methods rely upon the concept of channel width mod- ulation to modify the thermal behaviour of a microchannel liquid-cooled heat sink. At the heart of both these methods is a new semi-analytical mathematical model for heat transfer in liquid-cooled ICs. Such a mathematical model enables the application of gradient descent approaches, such as non-linear programming, in the search for the most optimally performing channel design in a huge multi-dimensional design space. In this paper, we thoroughly quantify the impact and efficiency of the semi-analytical model, combined with non-linear pro- gramming, when compared against several numerical optimiza- tion mechanisms. Our experimental evaluation shows that non- linear programming, alongside the semi-analytical model, is up to 23x faster than conventional randomized/heuristic design approaches such as genetic algorithms and simulated annealing using fully-numerical thermal models. Categories and Subject Descriptors 1.10 [Three-Dimensional Electronics]: Keywords Liquid-cooling of ICs, design optimization, channel width mod- ulation 1. Introduction Demands for high-performance and energy-efficiency in com- puting have encouraged research efforts in the development of compact liquid-cooled thermal packages for integrated cir- cuits. Specifically, liquid cooling using intertier microchannels in stacked three-dimensional integrated circuits (3D ICs) has garnered interest in the recent years [1, 2]. Liquid-cooling has been chosen over air-cooling in high-performance thermal pack- ages due to the superior thermal properties (thermal conduc- tivities and heat capacities) of liquids compared to gases. Sil- icon microchannels here are etched directly on the back-side of individual IC dies before stacking them one over another and finally hermetically sealing the entire package, as shown in Fig. 1. Significant progress has been made in the development and validation of such advanced thermal packages [3,4]. Large-scale adoption of liquid-cooling technology in electron- ics is only possible if design methodologies are in place that en- * This work was partly funded by the EC FP7 STREP Green- DataNet project (no. 609000), and the YINS RTD project (grant no. 20NA21 150939) evaluated by the Swiss NSF and funded by Nano- Tera.ch with Swiss Confederation financing. Figure 1: Stacked 3D IC with liquid cooling. able an early-stage temperature-aware exploration of the design- space and the optimization of various design parameters to pro- vide a desired thermal response. Here, the term “temperature- aware” design or exploration indicates the inclusion of temper- ature or thermal response of the ICs as an important design metric during the design-space exploration in addition to the conventional metrics of electrical performance and energy con- sumption [5]. Such thermal-management methodologies can then be coupled with the existing vast pool of design-space ex- ploration tools for performance enhancement and power man- agement -such as floor planning, routing and DVFS (dynamic voltage and frequency scaling)- to obtain a holistic design cy- cle that realizes the full potential of this technology. Already, efforts have been made towards this end with the proposal for new compact thermal models for IC liquid cooling [6,7] specifi- cally meant for early-stage design. In addition, various dynamic thermal management schemes involving flow-rate control have been proposed to improve the energy-efficiency of microchannel liquid-cooling [8, 9]. However, there is one avenue of optimized design specific to microchannel liquid-cooling that has not yet been fully ex- plored but has the potential to open up various dimensions in early-stage temperature-aware design space exploration: chan- nel width modulation. Channel width modulation entails the modification of the microchannel widths from inlet to outlet in specific forms and patterns to influence the heat-removal at different parts of the IC surface. The motivation for this comes from the well-known dependence of the local heat trans- fer coefficients on the aspect ratio of the microchannels [10]. By keeping the height of the microchannels- which is a func- tion of the etching process during fabrication- constant, it is possible then to vary the microchannel widths from inlet to outlet to change the local aspect ratios (and hence the local heat removal capability) along the channel. It has minimal manufacturing overhead since it only involves using modulated channel masks instead of straight channel masks during the etching process. Using channel width modulation, thus, it is possible to obtain any desirable thermal property of the heat sink. [11] was the first attempt at using this concept to minimize temperature hotspots on the chip. But the methodology pro- posed here relies on heuristic metrics on increasing/decreasing channel widths with respect to the positions of hotspots along the channel and does not offer a robust solution to minimize a particular design cost (for eg. temperature gradients) by taking into account other design constraints (for eg. pressure-drops or pumping power). We present two state-of-the-art applications of performing ro- bust design optimization using channel width modulation: Ap- plication 1 [12] that minimizes on-chip temperature gradients and Application 2 (GreenCool) [13] that minimizes pumping en- 978-1-4799-5267-0/14/$31.00 ©2014 IEEE 296 14th IEEE ITHERM Conference