IJARCCE ISSN (Online) 2278-1021 ISSN (Print) 2319-5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 8, Issue 6, June 2019 Copyright to IJARCCE DOI 10.17148/IJARCCE.2019.8612 60 A Novel Architecture for Multiplier and Accumulator unit by using Parallel Prefix Adders N. R. Nagarajan 1 , T. Muruganantham 2 , S. Rajapriya 3 Assistant Professor, Department of ECE, K. Ramakrishnan College of Engineering, Samayapuram, Trichy 1,2,3 Abstract: MAC unit is mostly demanded in the DSP application. It performs the both addition and multiplication. Here the MAC unit is designed by using the parallel prefix adders like kogge-Stone adder, Brent-Kung adder, Han-Carlson adder and Ladner Fischer adder these adders are the high-speed adders to improve the speed of MAC unit and multiplication purpose. In this design, these four adders are implemented to the array multiplier and to design the MAC unit. The performance and analysis of MAC unit is done by the Verilog HDL and the MAC unit is simulated and synthesized in Xilinx ISE 14.7 for Spartan-6 family technology. The simulation results show that low power, high speed and low area consumption MAC unit. Keywords: MAC, HDL, Fast Adders, DSP I. INTRODUCTION In recent years, Multiply-Accumulate (MAC) unit is developing for various high-performance applications. MAC unit is a fundamental block in the computing devices, especially Digital Signal Processor (DSP). MAC unit performs multiplication and accumulation process. Basic MAC unit consists of multiplier, adder, and accumulator. MAC unit model is designed by incorporating the various multipliers such as Array Multiplier, Ripple Carry Array Multiplier with Row Bypassing Technique, Wallace Tree Multiplier and DADDA Multiplier in the multiplier module and the performance of MAC unit models is analyzed in terms of area, delay and power. II. DESIGN OF MAC UNIT In Digital Communication, Digital Signal Processor (DSP) is an important block which performs several digital signal processing applications such as Convolution, Discrete Cosine Transform (DCT), Fourier Transform, and so on. Every digital signal processor contains MAC unit. The MAC unit performs multiplication and accumulation processes repeatedly in order to perform continuous and complex operations in digital signal processing. MAC unit also contains clock and reset in order to control its operation. Many researchers have been focusing on the design of advance MAC unit architectures. Figure 1: Block diagram of MAC unit III. DESIGN OF ADDER ARCHITECTURE Different adders that can be used for the design of a MAC unit are ripple carry adder, carry save adder and carry look ahead adder. Ripple adder is a regulararrangementofsinglebitadderswhichisbeingusedtraditionally.Inthe design the carry- output of one stage is connected to the carry-input of the next stage. Propagation of the carry generated by the fulladder circuits is avoided using the carrysave adder logic. The circuits ends the intermediate carries towards the outputs. Like ripplecarry adder it does not propagate the carry to the next stage.