DESIGN OF DYNAMIC COMPARATOR WITH A SENSITIVITY OF ½ V LSB FOR AN 8-BIT SAR ADC IMPLEMENTED IN 65nm TECHNOLOGY PROCESS Nel John S. Rosario and Allenn C. Lowaton Microelectronics Laboratory, Department of Electrical Engineering and Technology Mindanao State University - Iligan Institute of Technology Iligan City, Philippines neljohnrosario@gmail.com and allen.lowaton@g.msuiit.edu.ph Abstract— This paper presents a design of a design of dynamic comparator with a sensitivity of ½ VLSB for an 8-bit SAR ADC implemented in 65nm technology process. The proposed design can discriminate ½ VLSB with a minimum input difference of 0.8mV. The design was based on the modified two-stage latched comparator added with a cross-coupled control transistors. The proposed design has been simulated in Synopsys Custom Designer using TSMC65nm CMOS technology with a 1V supply voltage. It has a dimension of 19.28 um x 10.54 um. The total chip area for the layout is 0.2032112 nm 2 . Index Terms— dynamic comparator, successive approximation register, high sensitivity I. INTRODUCTION Comparator is one of the basic building blocks in the most analog-to-digital converters (ADCs). Many applications, such as memory sending circuits and on chip transceivers etc. are widely using comparators [1]. Many high speed ADCs such as flash ADCs require high-speed, low power consumption with small chip area [2]. With the reduction of power supply value and of transistor dimensions, amplifiers are becoming more difficult to design. Therefore, there is an increasing interest in ADC topologies not requiring amplifiers, but only comparators as in the SAR and Flash topologies [3]. The comparators operate in parallel and only one clock period is necessary to have the conversion result [4].In some sorts of ADC, the comparator has a great impact on the performance of the whole ADC. However, in some cases the error produced by the comparator can be compensated in the followed digital processing block [5]. Dynamic regenerative comparators are used to begin with, dynamic signifies the addition of clocks to the input of the circuit design. Regenerative comparators are those comparators using positive feedback like a latch to compare the signals. The feedback aids in providing higher speed in the circuit [6]. A comparator generates a logic output high and low based on the comparison of the analog input with a reference voltage. In an ideal comparator, with infinite gain, for input voltages higher than the reference voltage, the comparator outputs logical one and for the input voltages lower than the reference voltage it produces zero at the output[5]. Figure 1. Overall SAR ADC System [10] The sample-and-hold contains a switch and a capacitor. In the tracking mode, when the sampling signal is high and the switch is connected it tracks the analog input signal. Then it holds the signal when the sampling signal turns to low in the hold voltage [10]. The output of the sample-and-hold will then be passed to the comparator. The comparator is the analog block of a SAR ADC and performs the actual conversion. It compares the analog sampled input to the analog output of the DAC and generates the digital output of ‘0’ or ‘1’ which will then be used in the SAR logic [10]. The SAR logic determines each bit successively. In the first step, MSB is set to ‘1’ and other bits are reset to ‘0’, the digital word is converted to the analog value through DAC. Based on the comparator result, the SAR controller defines the MSB value. If the input is higher than the output of the DAC, the MSB remains at ‘1’, otherwise it is reset to ‘0’ [10]. The DAC converts the digital word at the output of the SAR logic to an analog value.