202 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 2, FEBRUARY 2002 Synchronization Circuit Performance David J. Kinniment,Alexandre Bystrov, and Alex V. Yakovlev Abstract—Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two indepen- dently timed regions. The mean time between failures (MTBF) is assumed to be , where , and are the clock frequencies on either side of the interface, and are constants. Here, is the time allowed for the synchronizer circuit to reach a stable value after clocking. Previous experimental work has shown that the slope of the histogram relating the logarithm of failure probability to is not always constant. We show that these effects, which include an apparent reduction in the value of in the early part of the histogram to as much as 60% of the final value, can be explained by extending the existing theory to take account of initial offsets, and we propose a new, more accurate, formula: , where , , , , and are circuit constants. Synchronizer performance depends on achieving a high reliability of synchro- nization together with a short time. We show that commonly used circuits, such as the jamb latch, do not produce the best compro- mise for very high reliability applications, and that a circuit with a lower value of can be designed. In order to confirm that thermal noise does not influence the MTBF against synchronization time relationship, we have devised an experiment to measure noise in an integrated CMOS bistable circuit. We show that the noise exhibits a Gaussian distribution, and is close to the value expected from thermal agitation. Index Terms—Analysis, design, digital, large-scale integration. I. INTRODUCTION S YNCHRONIZATION of digital data paths in submicron technology is of interest, because system failure may result from metastability in the synchronizer circuits, [1]–[3]. One as- pect of this problem that is becoming increasingly important is the design of synchronization circuits for multiply clocked systems, or for globally asynchronous locally synchronous systems. The frequency of failure in synchronizers using bistable de- vices is determined by the probability of marginal input trig- gering conditions, and the resulting mean time between failures (MTBF) of the system is dependent on the clock frequencies on either side of independently timed interfaces, , and , the number of synchronizers, and the response time of the circuit, . The MTBF, for an individual synchronizer, is represented by: , [1], [2] and includes a parameter , which may not be constant. Future systems will have clock rates of over 1 GHz, and the number of interfaces between separately timed zones, and therefore synchronizers, is likely to be high be- cause of the difficulty of clock distribution. The time allowed for synchronization must be kept as short as possible to main- tain system performance, but in order to keep system failures to Manuscript received March 7, 2001; revised August 24, 2001. The authors are with the Department of Electrical and Electronic Engineering, University of Newcastle, Newcastle NE1 7RU, U.K. (e-mail: david.kinniment@ ncl.ac.uk) Publisher Item Identifier S 0018-9200(02)00673-X. (a) (b) Fig. 1. (a) Gate small signal model. (b) Bistable. less than 1 in 10 s (2 years), may need to be over 30 . Con- trol of failure rates therefore depends on a good understanding of the synchronizer MTBF formula. Previous theory assumes a constant value and for all conditions, but recent results sug- gest that this is not the case [2], differing values of slope having been observed for different inputs. It is apparent that large inputs can drive the circuit away from the metastable point and while it settles, the value of may be apparently higher or lower than normal. Our aim is to analyze typical synchronizer and arbiter circuits and show how the results can be accounted for within accepted theory, and consequently, how synchronizer circuits can be de- signed for optimum performance. In this paper, Section II will develop the basic theory to account for different output thresh- olds and initial conditions, and Section III will compare this theory with simulations of practical circuits and present results of measurements on the circuits themselves. In Section IV, noise measurements are given, and in Section V, we will discuss the results, and the implications for system designers. II. MODEL Most models of bistable circuits operating as synchronizers assume that the cross-coupled gate circuits operate as two linear amplifiers [4]–[6]. Each gate is represented by an amplifier of gain and time constant , as shown in Fig. 1. Differing time constants due to different loading conditions may also be taken into account [6]. The model for each gate is linear with a gain and has an output time constant determined by . In a synchronizer, both the data and clock timing may change within a very short time, but no further changes will occur for a 0018–9200/02$17.00 © 2002 IEEE