MIXED SIGNAL LETTER Low quiescent current capacitorless small gain stages LDO with controlled pass transistors Sadeque Reza Khan 1 • Iram Nadeem 2 Received: 29 August 2017 / Revised: 17 December 2017 / Accepted: 26 December 2017 / Published online: 30 December 2017 Ó Springer Science+Business Media, LLC, part of Springer Nature 2017 Abstract A low quiescent current 180-nm output-capacitorless low-dropout regulator with small-gain stages (SGSs) is presented in this paper. The proposed technique permits the regulator to distribute the load current into two power transistors depending on the demand of the load using a controller based on load variation criterion. SGSs are introduced to enhance loop gain without low-frequency poles. The proposed architecture does not require compensation capacitor. Thus, the active chip area is reduced to 73.59 lm 9 36 lm. The measured results have shown that the fabricated circuit consumes a quiescent current of 1.8 lA at no load, regulating the output at 1 V with maximum output current of 50 mA from a voltage supply of 1.2 V. It achieves full range stability from 0 to 50 mA load current at a maximum 100 pF load capacitor. Keywords LDO regulator Á Capacitorless Á Quiescent current Á Pass transistor Á Small gain stage 1 Introduction Power management unit is an important part in the modern electronic systems. Recent system on chip (SoC) applica- tions require several voltage regulator-based power man- agement system to operate numerous functioning blocks [1]. Generally, low-dropout (LDO) voltage regulator hav- ing less output ripple is an ideal choice, especially for high performance and sensitive analog/mixed-signal blocks and radio frequency identification (RFID) application [2]. However, lower efficiency is the primary drawback of LDO regulators. Further, a typical LDO regulator uses large off-chip capacitor in the range of lF for stability requirements [3–7]. Although, the elimination of the off- chip capacitor raises challenges such as degrading the dynamic performance of the LDO in front of fast load transients. Therefore, the demand for capacitorless (CL)- LDOs for SoC applications is inevitable [8] where low area is a major performance scale for the applications such as biomedical implantable electronic devices. In addition, low power consumption is a very critical requirement for such devices. Thus, low voltage and low quiescent current are the most desirable parameters to achieve against loop sta- bility and transient response performance metrics. Several CL-LDOs have been demonstrated in the recent years [8–12]. In [9], a capacitor multiplier stage to improve the dynamic performance of the LDO, at the expense of power consumption is presented. The LDO reported in [10] has simple flipped voltage follower (FVF) structure which suffers from weak load and line regulations. The LDO regulator in [10] with a simple folded structure can be made stable easily in exchange of loop gain which affects the load regulation of such structures. In [11], a faster settling time-based design is demonstrated but it con- straints with larger undershoot and overshoot which makes this architecture improper in some applications. The architecture presented in [12] demonstrates the capability of switching between two and three stages depending on the load requirement with respective power transistor. However, at full-load condition the LDO suffers from high quiescent current, therefore, the circuit demonstrates poor load and line regulations. A local common-mode feedback & Sadeque Reza Khan srk5@hw.ac.uk Iram Nadeem engineer.iram@gmail.com 1 Institute of Sensors, Signals and Systems, School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh, UK 2 Department of Information and Communication Engineering, Chosun University, Gwangju, South Korea 123 Analog Integrated Circuits and Signal Processing (2018) 94:323–331 https://doi.org/10.1007/s10470-017-1103-3