G Rajesh et al., International Journal of Advanced Trends in Computer Science and Engineering, 9(3), May – June 2020, 2893 – 2898 2893 ABSTRACT Propagation delay and leakage power are the two major designing challenges in VLSI circuits, in sub-micron technologies. The paper presents here a novel dynamic charge sharing comparator with a technique: Low Voltage Power Reduction Technique(LVPRT), to decrease the propagation delayand leakage power. This comparator shares a charge to get approximately half of the supply voltage at both the outputs. The conventional analog comparators are occupies larger area due to their chain of pre-amplifiers, where as the design of dynamic comparators can avoid the general structure of chain pre-amplifier, therefore lesser area can be occupied, which in turns make us to achieve lower power consumption. The comparator proposed here has been simulated in CMOS 90nm technology node with constant supply voltage of 1V, at frequency of 100MHz using CADENCE Virtuoso tool and comparative analysis has been done with previous work. Simulation results shows that the power reduction of 66.87% and Propagation delay of 51.39% compared to previous work. Key words :Charge Sharing, Dynamic Comparator, Leakage Power, Propagation Delay. 1. INTRODUCTION Comparator plays major role in several application like data transmission, power regulators, zero crossing detectors, peak detectors etc. It can compare two inputs and gives a single output based on input voltage(V in ) and reference voltage(V ref ). If V in ˃ V ref, the output becomes “1” otherwise “0”. The major factors while designing of comparator are speed, power and area. Many Analog to Digital Converters(ADCs) that are especially used in portable devices have limited power supply energy uses the comparator. The conventional analog comparators are occupies larger area due to their chain of pre-amplifiers, so higher power consumption and lower speeds. However, when we go for the sub-micron technologies the threshold voltage of the CMOS devices are not shrinks same rate as the technology [1]. Which leads to increasing the complexity of the comparator design at lower supply voltages. Besides, the design of dynamic comparators can avoid the general structure of chain pre-amplifier, therefore lesser area can be occupied, which in turns make us to achieve lower power consumption. The general idea of designing dynamic comparators are either outputs are charged V dd or discharged to gnd. The overview of the several dynamic comparators, such as double tail comparators, differential pair comparator, Lewis-Grey comparator resistive diode comparator, and dynamic latched comparatorare discussed in [2]. These CMOS dynamic comparators uses the regenerative inverter latch structure to convert the small change in input signal, which in turns achieve low power and high speed [3]. These dynamic comparators works in the two phases called: (1) Pre-charge phase (2) evaluation phase. In phase one, the output capacitors outp and outnare charged to V dd. In phase two, the outputs outp and outn are conditionally discharges based on the input and reference voltages [4]. Figure 1 shows the taxonomy of comparator. There are many comparator which uses charge sharing logic[1,5-8], Where the NMOS pass transistor is used in pre-charge phase to share a charge between outputs outp and outn with approximately equal to half of supply voltage(V dd ). The output capacitors should not go less than threshold voltage.Which leads us to comparing of input signals becoming speed ups. Figure 1:Taxonomy of the Comparator Design of High Speed and Low Power Differential Voltage Charge Sharing Comparator using Small Swing Domino Logic G Rajesh 1 , Dr. JVR Ravindra 2 1,2 Dept. of Electronics and Communication Engineering, Vardhaman college of Engineering, Hyderabad, India. Email: rajeshbalija481@gmail.com; jvr.ravindra@vardhaman.org ISSN 2278-3091 Volume 9, No.3, May - June 2020 International Journal of Advanced Trends in Computer Science and Engineering Available Online at http://www.warse.org/IJATCSE/static/pdf/file/ijatcse62932020.pdf https://doi.org/10.30534/ijatcse/2020/62932020