S.Sasikala et al., International Journal of Advanced Trends in Computer Science and Engineering, 9(3), May – June 2020, 3793 – 3797 3793 ISSN 2278-3091 Volume 9, No.3, May - June 2020 International Journal of Advanced Trends in Computer Science and Engineering Available Online at http://www.warse.org/IJATCSE/static/pdf/file/ijatcse197932020.pdf https://doi.org/10.30534/ijatcse/2020/197932020 ABSTRACT In this paper, a hybrid multiplier circuit design employing hybrid logic style compared with transmission gates is reported. Multipliers play a crucial role in VLSI signal processing and various different applications. Area, Speed and Power are the fundamental factors in any VLSI systems. The primary goal is to enhance the general performance parameters of the multiplier such as delay, power and transistor count in comparison with the existing multipliers. The key role of hybrid logic approach is to take advantage of the features of numerous styles in an effort to enhance the general performance. The hybrid logic style including very susceptible CMOS inverters coupled with transmission gates is used inside the proposed circuit which offers high performance and occasional power design. Design metrics together with the speed, power and count of transistor are taken into consideration. All the circuits were designed the usage of Microwind device and simulated in 90nm technology. From the simulation consequences, it is determined that there's 53.4% reduction of energy and 38.9 % reduction of delay in the proposed multiplier for 1.2V power supply while compared to the present multiplier the use of transmission gates with 90nm technology. Key words : High speed, hybrid design, low power, transmission gates, weak inverters. 1. INTRODUCTION Multipliers play a crucial role in cutting-edge virtual signal processing and various different packages. High speed multiplier is the essential constructing block in a DSP system. Parallel multipliers are used for figuring out the high speed multiplication on the way to lessen the general power consumption of the DSP. It's far greater essential to reduce the energy dissipation of the parallel multipliers. Numerous techniques had been developed to reduce the strength consumption of parallel multiplier. Parallel multipliers are realized as array type shown in Figure 1 or tree type architectures. Distinctive logic styles each having its personal merits and bottlenecks, turned into investigated to implement hybrid multipliers[8]-[11][13]. Multipliers are built using the binary adders and full adders, that is one of the maximum essential building block of all of the afore mentioned circuit programs [4] and half adders. The designs are broadly categorized as Static style and Dynamic style. The on-chip region requirement is high in static full adders even as compared with its dynamic counterpart. Static full adders are generally greater dependable, easier with a good deal less power requirement .The conventional domain has vital logic styles which includes static CMOS [8] CPL[5][9] dynamic CMOS logic[10]TGA[1][2] More than one logic style referred to as hybrid logic design for the implementation is used for the alternative adder designs. To enhance the overall performance of the full adder these designs exploit the capabilities of various logic styles. CPL using 32[5] transistors show favorable voltage swing recovery. Despite the fact that, CPL is not appropriate for low strength applications because of its immoderate transistor be counted and overloading of its inputs. Both NMOS and PMOS transistors are blended the use of parallel logic styles in transmission gates. Low power CUK converters were proposed in [14]. When performance was compared, transmission gate circuit consumed less power as compared to CPL using CMOS logic style. Improving the various performance parameters like delay, power, and count of transistor of the multiplier in comparison with the existing ones is the main objective. The circuit becomes carried out using 90-nm generation by means of the usage of Microwind tool. The common power consumption (0.534 mW) of the proposed circuit become decreased via the usage of very vulnerable CMOS inverters added with strong transmission gates of 1.2 V which is used for designing hybrid multipliers. Figure 1 shows the basic 4X4 array multiplier structure. Performance Analysis of a Low-Power High-Speed Hybrid Multiplier Circuit Dr S.Sasikala 1 , S.Gomathi 2 , M.Kanimozhi 3 , K.S.Lakshana 4 , R.Karthik 5 1 Associate Professor, 2 Assistant Professor, 3,4,5 Student Department of Electronics & Communication Engineering, Kongu Engineering College, Perundurai, India. sasikalapriyaadarsan@gmail.com, samgomathi@gmail.com