V J Ylaya, International Journal of Advanced Trends in Computer Science and Engineering, 9(3), May – June 2020, 4113 – 4116 4113 ABSTRACT Presented in this paper are a comparison of a conventional full adder circuit and an improved design of binary full adder. The improved full adder circuit consists of 10 transistors reducing the area utilization of about 76.18% from the total standard area of binary full adder design. The overall design has an average power consumption of 2.94uW while achieving the full swing comparing to the 13.2mW power dissipation of conventional 28 CMOS Full Adder transistors architecture. The operating voltage used in this design is 1.2V and the modified binary full adder is designed and implemented in TSMC 65nm CMOS Technology. Key words: Binary Full Adder, Conventional 26T CMOS Full Adder, Adder 1. INTRODUCTION Full adder circuit is the core of many digital and analog circuits. It is a critical module for the operation of complex arithmetic operation such as addition [1]. Improving the performance of adder is essential. The main aim of designing the arithmetic circuit is to reduce power consumption and increase speed [2]. Several papers have investigated different approaches in realizing full adders using CMOS technology. At the same time, most tend to use the conventional structure [3]. Table 1. Truth Table for a 1-bit adder A B C in Su m C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 The objective of this work is to improve the conventional full adder. Performance criteria considered for design comparison include the area, delay, and power consumption as it is regarded as the main aim in designing arithmetic circuits [5]. The goal of a full binary adder is to implement the following truth table for each bit. In a binary adder circuit, A B and Cin act as input bits with SUM and CARRY that act as outputs SUM = (A ⊕ B) ⊕ Cin (1) Cout = ( A.B ) +(Cin. (A ⊕ B)) (2) 2. RESEARCH METHODOLOGY A basic architecture design was the basis of standard binary full adder design based on conventional CMOS full adder 2.1 Conventional Full Adder Architecture The conventional full adder design consists of 28 transistors. The structure poses several disadvantages – the presence of a series of transistors causes the adder to have the poor driving capability, and it occupies more area due to several transistors [6]. Figure 1: Conventional CMOS Full Adder Improved Design of Binary Full Adder V J Ylaya 1 1 College of Engineering and Information Technology, Surigao State College of Technology, Philippines. vylaya@ssct.edu.ph ISSN 2278-3091 Volume 9, No.3, May - June 2020 International Journal of Advanced Trends in Computer Science and Engineering Available Online at http://www.warse.org/IJATCSE/static/pdf/file/ijatcs239932020.pdf https://doi.org/10.30534/ijatcse/2020/239932020