International Journal of Electrical and Computer Engineering (IJECE) Vol. 10, No. 3, June 2020, pp. 2313~2321 ISSN: 2088-8708, DOI: 10.11591/ijece.v10i3.pp2313-2321  2313 Journal homepage: http://ijece.iaescore.com/index.php/IJECE Accurate leakage current models for MOSFET nanoscale devices Abdoul Rjoub 1 , Mamoun Al-Mistarihi 2 , Nedal Al Taradeh 3 1 Department Computer Engineering, Jordan University of Science and Technology Irbid, Jordan 2,3 Department of Electrical Engineering, Jordan University of Science and Technology Irbid, Jordan Article Info ABSTRACT Article history: Received May 31, 2019 Revised Nov 25, 2019 Accepted Dec 9, 2019 This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) was investigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper. Keywords: Gate induced drain lowering Leakage current mechanisms Low power devices Short channel effect Subthreshold leakage current Copyright © 2020 Institute of Advanced Engineering and Science. All rights reserved. Corresponding Author: Abdoul Rjoub, Computer Engineering Department, Jordan University of Science and Technology, University Campus, Irbid 22110, P. O. Box. 3030, Jordan. Email: abdoul@just.edu.jo 1. INTRODUCTION Recently, nanoscale CMOS devices have a tremendous demand for low power/high-performance applications [1]. This demand will remain increasing because of the promising electrochemical properties of Si semiconductor, among those properties, low power, high-performance operation, high-speed switching, and its immunity to physical variation [2]. Meanwhile, various literatures studied the nanoscale CMOS transistor's behavioral and proposed fast models for circuit simulations [3]. The leakage current is the main unwanted rate of current flow through the three main terminals of MOSFET transistor (Source, Gate, and Drain). This current is caused by the Short Channel Effect (SCE) and affects the overall behavior of the transistor. There are five types of gate leakage which are the parasitic gate leakage from the Gate to S/D Overlap region (I GO ) and which creates two currents (I GSO ) and (I GDO ), the Gate to the Inverted Channel Leakage (I GC ) which have two parts (I GCS ) and (I GCD ), and the Gate to the Substrate Leakage current (I GB ) [4]. The Band-to- Band tunneling current is caused by the high electric field during the standby node between the drain and the depletion layer. The higher value of the drain voltage (> depletion layer voltage) allows the electrons to tunnel from the reverse PN junction between the drain and depletion layer with a density depends on the applied voltages, the depletion layer depth, doping concentrations, and other factors that are discussed later. The higher complexity of calculating the integrals to find the value of tunneling leakage makes the importance of various approximations such as the rectangular approximation to find the values of the electric field and leakage current at any point of the irregular PN junction [5].