International Journal of Electrical and Computer Engineering (IJECE) Vol. 7, No. 6, December 2017, pp. 3323~3331 ISSN: 2088-8708, DOI: 10.11591/ijece.v7i6.pp3323-3331  3323 Journal homepage: http://iaesjournal.com/online/index.php/IJECE 250 MHz Multiphase Delay Locked Loop for Low Power Applications Shruti Suman 1 , K. G. Sharma 2 , P. K. Ghosh 3 1,3 Departement of Electronics and Communication Engineering, College of Engineering and Technology, Mody University of Science and technology, Lakshmangarh, Rajasthan, India 2 Departement of Electronics and Communication Engineering, Chandigarh College of Engineering and Technology, Chandigarh, India Article Info ABSTRACT Article history: Received Mar 17, 2017 Revised Sep 8, 2017 Accepted Sep 20, 2017 Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 MHzcenter frequency with locking range from 0.5 MHzto 250 MHz. Keyword: Delay locked loop Voltage controlled delay line Differential pair configuration Phase frequency detector Charge pump Loop filter Copyright © 2017 Institute of Advanced Engineering and Science. All rights reserved. Corresponding Author: Shruti Suman, Departement of Electronics and Communication Engineering, College of Engineering and Technology, Mody University of Science and Technology, Lakshmangarh, Sikar, Rajasthan, India. Email: shrutisuman23@gmail.com 1. INTRODUCTION In the era of recent development in deep submicron technologies, requires high operating frequency of VLSI systems and subsystems. High speed ICsrequiresproperlysynchronized on-chip clock signals for their operation. For clock synchronization operation in microprocessors and memory ICs, delay locked loop (DLL) and phase locked loop (PLL) are used to diminish the effect of jitter and skews of clock signals [1]. In DLL, VCDL is used in place of VCO which makes it differ from PLL. If frequency multiplier operation is not needed then a DLL is preferred over PLL because of high stability, less locking time and no jitter accumulation [2],[3]. DLL has a wide number of applications such as clock generators in DRAM ICs, microprocessors, clock de-skewing circuits [4],[5]. Locking time, lock range and jitter performance, static phase error, low power consumption and immunity against process voltage temperature loading (PVTL) variations are the most important metrics of a DLL. A DLL can be realized by a number of architectures; analog and digital DLLs are the two most important types among them [6]. Analog DLLs have better performance in terms of jitter, layout area, power supply rejection ratio, power consumption and clock skew. This paper introduces a mixed mode DLL in which single ended differential pair based VCDL is used which provides high stability against temperature and power supply variations. The proposed circuit depicts superior performance in terms of speed, power consumption, and locking range. The organization of remaning four sections are starting with architecture of basic DLL followed by analysis of different blocks, simulation results and conclusion.