2977 Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL Tanaji M. Dudhane 1 , T. Ravi 2 1 Research Scholar, Sathyabama Institute of Science and Technology, Chennai, India. tmdudhane@yahoo.com 2 Research Supervisor, Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Chennai, India.ravivlsi123@gmail.com ABSTRACT In the new world of science and technology with the tremendous changes in electronic gadgets such as microprocessors and microcontrollers, becoming an important blocks of the electronics industry. For any processor, CPU has integral part which is ALU, responsible for the efficient work of the processor. This paper integrates the computing ability of 8 bit processor with 16 bit co- operative arithmetic and logic unit and 8by8 bit multiplication. In this technology, 8 bit processor keeps its ability with excellent input/ output control with maintaining its simple architecture and low power consumption. FPGA offers a platform for designing and implementing soft cores for improvement in execution time and developing IP cores. 16F84 RISC processor is designed module wise developed with HDL language and implemented using FPGA with enhanced architecture. The results are obtained in three ways as firstly designing and implementing 16 bit CALU with 8 bit processor, secondly 8by8 bit multiplier and thirdly combined integration of 16 bit CALU and 8by8 bit multiplier. Simulation result for 8 bit multiplier shows execution time of 109.241 ns, with 16 bit CALU is 674.66 ns and with multiplier and 16 bit CALU is 583.33 ns, 76.09 % cycle saving is achieved with the implementation using reconfigurable hardware, improving execution time from 674.66 ns to 583.33 ns. The design is configured on Xilinx 14.6 using FPGA and implemented using Verilog or HDL. Key words : ALU, CALU,8by8 bit, FPGA, RISC VHDL. 1. INTRODUCTION Normal approach of design is to reduce the machine cycles, variation in data bus width, reduction in cost and implementing using FPGA for better performance. In the modern technology of electronic design, FPGAs are the solutions for the core processors as well as for the different modules of the processors such as arithmetic and logic unit, multiplier, barrel shifter, MAC unit. PIC16 series of Microchip is popular for development of microcontroller using 4 states T1 to T4. Uses of Verilog or HDL languages ease the development for improvement in execution time of instructions. Modifying the size of program counter, additional instructions incorporated with 8 bit processor. System on Chip (SOC) has the important block as microcontroller with deep pipeline of 5 Stages. The pipelining stage having memory read and write back cycles, increments 67% in maximum clock rate with 86% increment in MIPS [1]. When a normal processor is integrated with maximum number of data lines for ALU, it enhances its computational ability. ALU is the important block of any modern processors, cause of its speed and size having major contributions in overall performance of the processor related to cost. Modern digital signal processors (DSPs) and Application Specific Integrated circuits (ASICs) were the solutions but having limited Space [2]. The use of 8 bit processor is suggested in Cellphones, PCs and robots with FPGA and in mathematical operations, the movement of data from one location to another is also suggested [3]. Now, PLDs (programmable logic devices) and CPLDs (complex programmable logic devices) are especially field programmable logic arrays (FPGAs), having their appearance in power electronics for modern control applications of conference paper in [4]. Device utilization is presented and integration concept is summarized in the conference paper [5]. The characteristics of FPGA, time to market, low price, low energy consumption and its use for implementing low to high end processors [6], is the work carried out by the author. FPGAs are suited for low-end to high-end processors. Design and development of processor of any kind using Verilog or HDL language on FPGA, is a solution for single chip processor and its different modules as ALU, control unit, decoder unit using combinational circuits as the example in the journal article in [7]. Reduced Instruction Set Computer is the design methodology for modern as well as pre-processors using FPGA, due to the increase in capacity of number of gates and processor performance in terms of speed and gate count [8]. While designing the processor, its instruction size also taken into consideration. Instruction length is minimized for minimum area occupation in memory. The length of the instruction is 22 bit wide, which acquires more area to store the instructions in the memory. Instead of using 22 bit size, we have designed 15 bits of instruction size from which, most significant bit (MSB) determines the operation of 8 bit or 16 bit ALU [9]. As example of journal article in [10], implements the CPU design and its mapping using FPGA. In ISSN 2347 - 3983 Volume 8. No. 7, July 2020 International Journal of Emerging Trends in Engineering Research Available Online at http://www.warse.org/IJETER/static/pdf/file/ijeter15872020.pdf https://doi.org/10.30534/ijeter/2020/15872020