Kakarlamudi Lakshmi Maidhili et al., International Journal of Emerging Trends in Engineering Research, 8(7), July 2020, 3386 - 3392 3386 ABSTRACT These days SOC became very essential part and it is a great revolution in electronics world. Basically, for any SOC or (IP) verification results are very important as we cannot predict that our chip we design will meet our expected performance or not. As a consequence, the failure of the SOC / IP is more common in development. SOC / ASIC verification begin as soon as architecture or micro architecture is established in any industry. This continuous procedure is structured to ensure the accuracy of the basic design specification prior to the tape-out. Product life cycle along with performance of the chip is prime factor in any electronic device. In order to increase our confidentiality of chip Gatesim that is Gate Level Simulations (GLS) are introduced in Verification era. Particularly the 14 nm technology nodes and below are responsible for much longer simulation run times and are also responsible for larger memory. As a result, in order to complete the testing specifications in time, it is extremely necessary for GLS to be started as early as possible in the design process and for the simulator to run in high-performance mode. In this paper we mainly focus on verifying reset test logic for Input Output Die (IOD) part of entire SOC is working as expected or not using Gate level simulation simply referred as Gatesim. Key words: SOC, GLS, Boot logic, Verification 1. INTRODUCTION In today’s electronic design automation Verification is very crucial. Functional verification is a necessary step in the development of today’s complex designs. Most of the Design and development cycle of an SOC or any IC is verification. Hardly verification is of 70% of product development cycle. Whereas 20 % is spent for implementation and rest 10% is for design part as shown in the bar graph in Figure 1. Figure 1: SOC design cycle SoCs are built by a large number of in-house and third-party IPs. The integration of multiple processor cores and IPs is a difficult task. It is even more difficult to verify the different scenarios that come with such complex designs. It has become essential to carry out a hardware-software verification to cover the functionalities presented by both hardware and software structures. Because SoCs usually require a minimum of one CPU, it is important to check and see how the CPU responds with different input stimulations. Confirmation of SOC/ASIC starts off evolved as quickly as structure or micro architecture is described in any type of region. This cyclic technique to ensure the useful correctness of the information layout specification before tape-out. Our checks are placed in RAM, and the processor reads as well as implements those recommendations. Generally we use C or CPP to write confirmation checks, compiled as well as converted into hex code especially for the processor being used, on the way to be filled proper into memory. We keep in mind that after energy-on and reset sequences are executed, the CPU assessments out boot code and additionally in the end start appearing instructions from RAM. System Verilog/UVM is used in validating IPs t block level verification [1][6]. A lot of precise checks are required at Chip level we require to compose precise checks at chip diploma to ship offers from the IP to the rest of the additives in the machine. Vector unit’s requirement to be created for every and every IP further to device level checks like safety, pad multiplexing, and so forth. Kakarlamudi Lakshmi Maidhili 1 , Fazal Noorbasha 2 , Allamsetty Vamsi 3 , Kakarla Hari Kishore 2 1 M.Tech Student, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, A.P, India. shinestarmaidhili@gmail.com 2 Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, A.P, India. fazalnoorbasha@kluniversity.in 3 Senior Silicon Design Engineer, Advanced Micro devices, Hyderabad, Telangana, India. vamsi.int@gmail.com Reset Logic Verification of an IOD at System on Chip Level using GateSim ISSN 2347 - 3983 Volume 8. No. 7, July 2020 International Journal of Emerging Trends in Engineering Research Available Online at http://www.warse.org/IJETER/static/pdf/file/ijeter82872020.pdf https://doi.org/10.30534/ijeter/2020/82872020