A Reversible-Logic based Architecture for Artiﬁcial Neural Network Bappaditya Dey 1,3 , Kasem Khalil 1 , Ashok Kumar 1 , Magdy Bayoumi 1,2 1 The Center for Advanced Computer Studies 2 Department of Electrical and Computer Engineering University of Louisiana at Lafayette, Louisiana, USA 3 imec (Belgium), Kapeldreef 75, 3001 Leuven, Belgium Emails: {kasem.khalil1, bxd9836, axk1769, mab0778}@louisiana.edu Abstract—High-performance computing beyond sub-10 nm ad- vanced node technology allows us to explore and use complex 2.5D/3D SOC design architecture. Node scaling, heterogeneous integration, and complex design enable us to think beyond Moore’s law but, at the same time, limit the scope with concerns of excessive power dissipation. The ﬁeld of quantum computation and reversible logic functions has been researched in recent years in the context of low power VLSI circuit designs and nanotechnology. Reversible computation exhibits signiﬁcantly reduced power dissi- pation in digital circuits. In this paper, we propose a novel design of Artiﬁcial Neural Network (ANN) using reversible logic gates. A thorough search of the relevant literature yielded only a few related articles. To the best of our knowledge, our proposed approach is the ﬁrst attempt to implement a complete feedforward neural network circuit using only reversible logic gates. The comparative analysis demonstrates that our proposed approach has achieved an approximately 16% reduction in overall power dissipation compared to existing approaches. The proposed approach also has better scalability than the classical design approach. Keywords: Reversible logic, Quantum computation, Deep neural network, Feedforward network, Low power circuits, Artiﬁcial neural network. I. I NTRODUCTION In recent decades, Node-technology scaling has already sur- passed beyond sub-10-nm as a result of combining exponential depiction of Moore’s law [1] with advanced node-technology. 3D SoC (System-On-Chip) design integration enables us to integrate a few billion transistors per CPU (Central Processing Unit) in recent years. A trade-off between high-performance computational efﬁciency and circuit complexity and cost can be optimized. However, excessive power consumption has emerged as a signiﬁcant bottleneck against high-performance computa- tion and was listed as a crucial challenge in ITRS (International Technology Roadmap for Semiconductors 2008). Low power VLSI design can be exploited at various levels of circuit design using various generic methods. In this paper, we have reviewed the quantum computation and reversible logic approach [2]. Any conventional digital operation is irreversible as it is impossible to derive input signal information from its corresponding output. For example, let us consider an example of a conventional irreversible AND gate. For any input bit as logic ‘0’, the corresponding output bit is logic ‘0’, and the output is logic ‘1’ only when both inputs are in logic ‘1’ state. Now, just by looking only at the output in logic ‘0’ state, it is impossible to derive which Input bit signal in logic ‘0’ (out of combination 0-0, 0-1, 1-0) state is computing the output as logic ‘0’. Signal information of length q-bit can be encoded into any one of the possible 2 q states. According to Landauer’s principle, loss of each information bit generates approximately KT ln2 (Joules) thermal energy in terms of power dissipation, where Boltzmann’s constant K =1.38 * 10 -23 (J/K) and T is the absolute temperature of the computation [3]. If we consider Apple A8X (tri-core 64/32-bit ARM64) as an example in our power dissipation calculation which crams approximately 3 billion transistors, under room temperature (T = 300K), for a single irreversible bit operation, we will approximately loose: Fig. 1: Generalized (N × N ) reversible logic functionality. P =(ln2 × 1.38 × 10 (-23) × 300) = (1) (1.38 × 300 × 0.6931471 × 10 (-23) ) × 3.0 B (2) =3.0 B × 2.86 × 10 (-21) J (3) Such lost of power becomes a signiﬁcant ﬁgure of merit in advanced node-technology. According to C.H.Bennett [4], the paradigm shift from classical irreversible digital gates to reversible logic gates enables us to avoid this signiﬁcant power dissipation loss. Reversible logic operations are lossless as we can perform a reverse order direct mapping (N-to-N) from any output signal to its corresponding input signal(s) [2, 5]. This paper proposes a novel design of a neural network hardware circuit using reversible logic, where neural network is used in many applications such as image classiﬁcation and intelligent hardware systems [6]. We have also compared our approach with existing conventional digital circuits in the context of quantum cost, power dissipation, and hardware complexity and garbage outputs. The remainder of the paper is organized as follows. In Section II, we have brieﬂy discussed an overview of Artiﬁcial Neural Network (ANN) and reversible logic gates. Section III introduces the proposed reversible logic-based neural network hardware architecture. Experimental result, comparative analy- sis, and discussions are presented in Section IV. In Section V, we have concluded the paper. II. OVERVIEW OF ARTIFICIAL NEURAL NETWORK AND REVERSIBLE LOGIC In this section, we have explained the basic concepts of reversible logic paradigm and discussed the evaluation indexes for a reversible logic circuit as garbage outputs, quantum cost, constant inputs, hardware complexity index and delay. A. Reversible function Any reversible functionality can be realized using a com- bination of different reversible logic gates. We have rep- resented a generalized block of reversible logic in Fig. 1 with N-dimensional input vector  I =(I 1 ,I 2 , ....,I N ) and N- dimensional output vector  O =(F 1 ,F 2 , ....,F N ) respectively. The basic realization of a reversible logic is 1:1 correspon- dence mapping between any arbitrary N-bit inputs and its N-bit outputs. As there is no loss of bit information during a reversible logic operation, any reversible functionality contributes ideally ‘0’ (Zero) amount of power dissipation. 978-1-7281-8058-8/20/$31.00 ©2020 IEEE 505 Authorized licensed use limited to: University of Louisiana at Lafayette. Downloaded on September 09,2020 at 16:52:30 UTC from IEEE Xplore. Restrictions apply.