Nano-Power Sensor Applications in VLSI Multi-Die Tiny Chip Shuza Binzaid 1 , Imran Chowdhury 2,3* , Md. Shoaibur Rahman 4 , Sheik Md. Kazi Nazrul Islam 2 1 University of Texas at San Antonio, Texas 78249, USA 2 University of Information Technology and Sciences (UITS), Dhaka 1212, Bangladesh 3 Convenient Energy Solutions, Dhaka, Bangladesh 4 The University of Asia Pacific, Dhaka, Bangladesh * last4first@yahoo.com Abstract— Semiconductor integration has improved over the years by increasing device switching speed and device density, causing increased power consumption and dissipation; therefore, the issues has been considered and improved here. Previously designed VLSI mirror-amplifier had power dissipation of 8.41 milliwatts in CMOS 0.5µm process. Latter the technique was re-applied in this work to completed characterization of each pin signal functions with biasing steps to determine accuracy at the low power response of the IC in order to improve the total power consumption. Signal pin orientation in the simulation and choosing the correct biasing point in two steps proved to be correct procedure to improve. Supply voltage was considered as 3V for the MOSIS process technology. Latest MAGIC layout CAD tools were used for design, and PSPICE was used for simulation and electrical characterization with the help of MAGIC layout extraction tool. Keeping the process and scaling unchanged at 0.5µm as the previous design, the new VLSI design yielded the power dissipation of 4.39 nanowatts in 2 nd step by reducing the dynamic loss. The electrical characterizations also confirmed that the chip precisely senses ultra-high-Z signals at inputs for this application. Multi-die chip placement is done for fabrication and also made the final product less expensive by the in-house custom designed pad-frame. This paper presents details of the key research works, results, completed chip layout and applications of the chip. Keywords—Nano-Power VLSI; Mirror-Amplifier; Mixed- Signal Applications; MOSIS Tiny-Chip; MOSIS CMOS Design; Multi-Die Placement. I. INTRODUCTION As MOS Integrated Circuits (ICs) have come to dominate analog, digital, and mixed-signal electronic circuit designs over the last 15 years [1], the pressure to reduce system cost has favored all-CMOS solutions over systems that mix bipolar and CMOS chips or use Bi-CMOS technology [2]. In current design practices, bipolar devices are usually found only in very-high performance wired and wireless designs, where extreme device specifications (high f t , low noise, and superior matching) require high-yielding, power-efficient components [3]. Similarly, compound semiconductor devices are used only in the case of very high-speed circuits in applications running at GHz level with low power [1]. With a continuing reduction of MOS transistor channel lengths, modern CMOS silicon processes offer transistor with a higher cut off frequencies [4]. So as it is known that CMOS technology is capable to implement radio frequency (RF) transceivers, recently many researches on radio frequency (RF) ICs in GHz-level-band have been accelerated because of the potential Industrial, Scientific, and Medical (ISM) band and the wireless vehicular radar applications [5-6, etc.]. CMOS processes that have been developed primarily for logic are now also used as amplifier and sensor [7]. Several researchers have presented CMOS amplifiers for an optical receiver with external photo detectors [8-10, etc.]. Most of these amplifiers depend on analog CMOS process technologies. Recently, there have been attempts to use standard digital CMOS technologies since there are more demands to have analog and digital circuits on same chip allowing a very high bandwidth and very low power at the same time [10]. Today’s electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high- volume products to be developed very rapidly. This, combined with advances in deep sub-micron technology has resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is very likely the chip will contain both analog and digital sections, which make the IC, design procedure a lot more complex [11]. The increasing complexity and decreasing feature size have made the demand of IC products more compact with more facilities and low power and fabrication cost. With this thought as a goal, this paper presents a proposal of nano-power mixed signal mirror- amplifier with its VLSI design that can be used as precision sensor. The proposed circuit is basically composed of two compact sense amplifiers placed as mirrors to each other for I/O. A NAND gate is placed in between these amplifiers’ outputs. Hence the designed chip is composed of both analog and digital signal handling capability. II. CIRCUIT DESIGN The Figure 1 represents the schematic of the mirror- amplifier circuit, which is designed by Dr. Shuza Binzaid. Construction of this circuit consists of two compact circuits of sense amplifiers creating mirror architecture and a NAND gate in between them. Analog inputs are placed at these sense amplifiers. The output is the NAND output here. Thus this circuit also becomes digital compatible. Thus it becomes a mixed signal chip. It contains total of 14 MOS transistors in which 6 of them are p-MOS (M1-M6), and rest 8 are n- MOS (M7-M14). The operation of the circuit is done by total