DESIGN AND ANALYSIS OF A COMPARATOR FOR ADC IN TANNER EDA Mohammad Rizwan B.Tech in Bapatla Engineering college, GBC Rd, Mahatmajipuram, Bapatla, Andhra Pradesh 522102. --------------------------------------------------------------------------***---------------------------------------------------------------------- ABSTRACT--- Flash ADC is the fastest ADC in the analog to digital conversion which is employed popularly in high-frequency applications. The comparator is a major block used in the flash ADC for analog to digital conversion. The use of comparators count is varied depends on the resolution of the flash ADC. Comparator count increases as 2n for an n-bit resolution flash ADC. As the resolution of the ADC increases, the use of comparator count in the ADC is also increased as large which increases the area utilization of the ADC. This paper analyzes the area and power utilization factor of the various types of comparators in order to solve the area utilization problem in the flash ADC. The comparator circuits are simulated in cadence virtuoso using CMOS 180nm technology. The power, area and delay of the different comparators are compared for best utilization in the flash ADC. Keywords— ADC, Comparator, Resolution, CMOS, Track and Latch, TIQ dissipation and the conversion performance. A low noise latch track comparator has been introduced in [1] for high- speed low power flash ADC applications. A random- chopping comparator has been introduced in [2] to reduce the offset by observing the code density of the comparator. All the calibrations are performed in the digital domain through the characterized probabilistic distribution of the analog input and reference voltage. Offset fluctuation has been reduced drastically in the method introduced in [3]. A threshold inverter quantization (TIQ) based comparator has been introduced in [4-5] for high-speed low area flash ADC applications. The TIQ comparator provides the voltage swing up to the supply voltage. TIQ-comparator quantizes the analog input data to the thermometer code. The TIQ method is modelled to set the threshold voltage by varying the channel length and width of the transistor. 1. INTRODUCTION Analog to digital converter (ADC) is the most frequently used analog and mixed-signal circuit for analog to digital data conversion in microprocessors and microcontrollers, DSP architectures, communication devices and consumer electronics applications. It is a strap between analog and digital processing techniques to process the real-world analog signal and to produce the equivalent digital outputs for fast and accurate processing in the high-performance digital devices. Flash types ADC is the fastest data converter which uses (2 N -1) number of comparators to simultaneously to compare the analog input voltage with the reference input voltages. In the flash ADC, the output of the comparator is obtained in the form of thermometer code and then using an encodes the thermometer code form of digital data converted into the binary outputs form. The flash ADC architecture does not require any linear amplification technique since it has the highest rate of the analog signal to digital data conversion speed at any given technology. In an ADC, many circuit techniques like folding, interpolation and sub-ranging are used in the implementation to reduce the power consumption and the area overhead of the circuit. The use of modified architecture for a flash ADC use to reduce the linearity of its transfer function due to the generation of the random offset voltage. The offset voltage is induced in the symmetric circuit configuration due to the mismatches of the transistors in the comparator circuit. This paper provides the detailed design and analysis of the linear comparators of the ADC for area overhead, power Latch-track comparators, Dynamic comparator, high- speed comparator, low power comparator and TIQ comparators are the popularly used comparators in the implementation of the flash ADC. A. Dynamic Comparators Usually, the use of a large number of comparators in the flash ADC increases the power dissipation. Dynamic comparator reduces the power dissipation of the ADC by eliminating the static power dissipation. The use of dynamic comparator in the ADC increases the value of offset voltage and reduce the gain of the circuit. In order to make a high speed and low power comparator, the preamplifier-based comparator is used in the high-speed comparator. A static mismatch developed in the comparator components due to the variations of the threshold voltage V Th and μ n C ox , are the critical issues in the comparators. A dynamic comparator proposed in Fig. 1 has a capacity to overcome the static mismatches present between the components. Although it has the advantage of low power dissipation but it suffers severely from the dependency of input evaluation on the common-mode input voltage (V cm ). In the differential amplifier of a high-speed comparator, observation of less common mode voltage is an attractive solution to increase common mode range. The double tail dynamic comparator is a popular circuit used with a different tail transistor for both pre-amplifier and latch stage to avoid the drawbacks like static mismatches and noise. A noise in the comparator 2. THE DESIGN STRUCTURE OF THE COMPARATORS International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 03 | Mar 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1276