International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 06 | June 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.529 | ISO 9001:2008 Certified Journal | Page 3862 Multilevel Half Rate Phase Detector with using Gate Diffusion Technique to Recover the Data and Clocks Kanagavalli S A 1 & Padma S I 2 & Mustafa Nawaz S M 3 1 PG SCHOLAR, PET ENGINEERING COLLEGE 2 ASSISTANT PROFESSOR, PET ENGINEERING COLLEGE 3 ASSISTANT PROFESSOR, PET ENGINEERING COLLEGE -------------------------------------------------------------------------***---------------------------------------------------------------------- Abstract – In the recent communication system of electronic industry will focusing on high speed signal processing application, with be assistance of optical to electrical data communications, multiplexing technique of TDMA, CDMA, OFDMA. Here this communication will required a high priority to recover clock and reduced jitter in clock and data with high performance synchronous operations such as the retiming and demodulation. Here this work will present a technique of Half-Rate (HR), Bang-Bang (BB), Phase Detector(PD) based multiple decision of clock and data recovery about the sign and magnitude of the phase shift between the PD inputs. Here, this proposed architecture will introduced a GDI (Gate Diffusion Input) technique and reduced the number of transistors in this data and clock recovery technique of HR-BBPD and ML-HR-BBPD at 90nm CMOS Technology with using DSCH3 and MICROWIND software and compared all the parameters in terms of Area, Delay and Power. Key Words: GDI (Gate Diffusion Input), Half Rate (HR), Phase Detector(PD), Bang Bang (BB), Multilevel (Ml), ML- HR-BBPD. 1. INTRODUCTION Clock and data recovery (CDR) is a key function in many serial communication systems, from optical to electrical communications, but especially for high-speed signaling. The performance of the clock recovery is crucial for the reliability of the communication system, especially important to perform synchronous operations such as the retiming and demodulation of the input data. Jitter in the clock, defined as the uncertainty in the edge placement in the clock waveform, results in distortion of the data signals waveforms. This jitter translates in oscillator phase deviation from ideal, which results in phase noise. Although other systems such as delay-locked loops or phase interpolator-based CDR are used in some cases, phase locked loops (PLLs) are the most widespread systems to implement a reference-less CDR. It is composed of a voltage-controlled oscillator (VCO), which generates the required clock, a phase detector (PD), which compares the phase of the generated clock to that of the randomized input data, and a charge pump (CP), which charges or discharges a loop filter (LF) to generate the required control signal for the VCO. The PD is one of the critical blocks of the CDR as it determines the phase error between the input data and the clock, which conditions the control voltage for the VCO, and therefore the correct agreement between the clock and data edges. Although a linear PD is sometimes used in a binary or bangbang (BB) PD is usually preferred in high-speed CDRs due to its simplicity, good phase adjustment, high- speed operation, and low power. The BBPD provides a binary output, which gives information about the sign of the phase shift between its inputs, i.e., if the clock is lagging or leading the input data The Alexander PD or variations of it, such as the inverse Alexander PD where the outputs (Early and Late) are inverted (Late and Early) are the most commonly used PD in highspeed designs. Other topologies have been presented but their complexity is increased. All these Alexander-based PDs work at a full-rate clock frequency; which means that the frequency of oscillation of the VCO is the same as the data rate of the input data. At high speed, a half-rate PD (HR- PD) is very useful to reduce the requirements of the VCO and increase the throughput of the system. CDRs implemented with an HR-PD sense the input data at full rate but use a VCO running at half the input rate. This technique also relaxes the speed requirement of the PD. In this brief, we propose a new multilevel HR BB PD (ML- HR-BBPD). Thanks to the ML operation that provides information about the sign and the magnitude of the phase difference between the PD inputs, the bit error rate (BER) performance of the output data as well as the jitter of the clock generated with a PLL-based CDR is improved compared to the conventional two-levels HR-PD. Although ML-BBPD have been already proposed in some PLL-based CDR with very interesting results, to our best knowledge, they have never been proposed for an HR system. The main objective of this brief is, therefore, to