International Journal of Electrical & Electronics Research. (IJEER) Volume 4, Issue 1, Pages 10-15, March 2016, ISSN: 2347-470X 10 Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture S. Munaf 1 Assistant Professor Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore- 641042, India shrivastavaanurag@rediffmail.com Dr. A. Bharathi 2 Professor Department of IT, Bannari Amman Institute of Technology, Sathyamangalam-638401, India shrivastavaanurag@rediffmail.com Dr. A. N. Jayanthi 3 Associate Professor Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore- 641042, India sudhir.732000@gmail.com Abstract— Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator. Keywords— Coarse- grained reconfigurable architecture, configuration cache, embedded system, loop pipelining, low power. 1. INTRODUCTION To provide high quality multimedia on mobile and embedded systems, efficient algorithms for audio/video data transfer and processing have been developed. These algorithms are complex and have computation- intensive and data-parallel characteristics. For such applications, two extreme approaches are used for their implementation: software running on a general purpose processor hardware in the form of application - specific integrated circuit (ASIC). In the case of general processor, it is flexible enough to support various applications but they may not provide sufficient performance to cope with the complexity of the applications. In the case of ASIC, one can optimize the implementation in terms of power and performance but they rely on application. A coarse-grained reconfigurable architecture (CGRA) can provide the advantage of both the approaches. CGRA has higher performance than general purpose processor and wider applicability than ASIC. In spite of the previous advantages, the deployment of CGRA is prohibitive due to its significant power consumption. This is due to incorporation of many computational resources such as algorithmic logic unit (ALU), multiplier, divider, and configuration cache to perform frequent memory read operations for dynamic reconfiguration in every cycle. The configuration cache is the main component in CGRA that provides distinct feature for dynamic configuration. Even though configuration cache plays an important role for high performance but suffers from large power consumption. Therefore, reducing power consumption in the configuration cache has been a serious concern for reliability of CGRA. For Low power CGRA design, this paper provides an optimized Low Power Technique in the configuration cache and its hardware implementation. In this paper, we suggest a novel power-conscious architectural technique called to Double Pumping Technique(DPT) reduce the data transfer time and also increase the operating speed and power consumption in configuration cache. DPT is universal approach in reducing power and enhancing performance for CGRA because it can be achieved by closing the power- performance gap between clock periods. High performance achieved increasing the data transfer rate. This has been demonstrated by using real application benchmarks and gate level simulations. This paper is organized as follows. After mentioning the related work in Section II, we discussed base architecture in Section III. In Section IV, we present the motivation of our approach. In Sections V and VI, we suggest power- conscious techniques based DPT. 2. RELATED WORK Many kinds of coarse-grained reconfigurable architecture have been proposed with the increasing interests in reconfigurable computing in recent years [1]. These CGRAs can be classified into two cases: mesh-based reconfigurable array and linear reconfigurable array. Mesh-based reconfigurable arrays arrange their processing elements (PEs) mainly as a rectangular 2-D array with both horizontal and vertical connections, which supports efficient parallelism. In the case of linear reconfigurable arrays, they support