IJSRSET207348 | Accepted : 20 May 2020 | Published : 29 May 2020 | May-June 2020 [ 7 (3) : 170-174 ] International Journal of Scientific Research in Science, Engineering and Technology (www.ijsrset.com) © 2020 IJSRSET | Volume 7 | Issue 3 | Print ISSN: 2395-1990 | Online ISSN : 2394-4099 DOI : https://doi.org/10.32628/IJSRSET207348 170 Robust 12T Sram Cell Using 45nm Technology N. Geetha Rani 1 , N. Jyothi 2 , P. Leelavathi 2 , P. Deepthi Swarupa Rani 2 , S. Reshma 2 1 Associate Professor, Department of ECE, Ravindra College of Engineering for Women, Kurnool, India 2 Department of Electronics and Communication Engineering, Ravindra college of Engineering for Women, Kurnool, India ABSTRACT SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation. Keywords : SRAM, Micro wind Software, Power consumption, Transistors. I. INTRODUCTION An exceptional growth is achieved by electronics industry over the last two decades, mainly due to the expeditious advances in integration technologies, due to the emergence of VLSI. The number of applications of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been progressing undeviatingly, and at a very instant pace. Typically, the required computational power of these applications is the driving exertion for the fast blooming of domain. The current leading-edge technologies (such as low bit-rate video and cellular communications) already provide the end-users a certain amount of processing power and portability. This trend is expected to continue, with very important implications on VLSI and systems design. One of the most important characteristics of information services is their increasing need for very high processing power and bandwidth. The other important characteristic is that the information services tend to become more and more personalized (as opposed to collective services such as broadcasting), which means that the devices must be more intelligent to answer individual demands, and at the same time they must be portable to allow more flexibility/mobility. As the SRAM cells are incorporated by latch, the refresh operation isn't required to keep the data during power on condition in SRAM cells. Every one of the systems like microprocessors, hand held gadgets, workstations have the cache memory which is outlined by SRAM cells due to its transistor favorable circumstances of giving quick exchanging and low power utilization. To store a single bit of data SRAM utilizes four transistors. The basic parameters of SRAM cells are the speed and furnishes multiple designs with the point of corrupting the power utilization during read write tasks of SRAM. By considering this need, in this paper some standard SRAM cell outlines viz. 6T, 7T,