1 The Performance and Behavioral of Dual Edge Triggered Flip-Flops in Nano-Technology Abdoul Rjoub 1 , Muna M. Al-Durrah 1 , 1 Department of Computer Engineering, Jordan University of Science and Technology, Irbid 22110, P. O. Box 3030, Jordan Abstract The influence of the Nano-Technology on the most frequent used Dual Edge Trigger Flip-Flops (DET-FF) is presented in this paper. The performance and behavioral of those Flip-Flops are discussed and analyzed analytically. Simulation results show that each time scaling down the SPICE parameters, some of the tested Flip-Flops did not work properly; it seems that the structure of the transistors and the internal nodes of those Flip-Flops using low supply voltage under Nano-Technology are the main barrier to operate properly. A new Low power, high speed DET-FF based on transmission gate is proposed as efficient DET- FF at the end of this paper, using 45nm SPICE parameters, simulation results show that the proposed DET-FF has low power and high speed at low supply voltage. 1. Introduction The nanotechnology scale became a fact in recent applications as noted by A.Raychowdhury and Roy (2006). Various references and papers are implemented using this feature of scale as shown in R. Ramanarayanan (2002). The main advantages of nanotechnology are the performance increasing and the supply voltage decreasing, this cause a reduction in the power dissipation and saving power. However, the main draw back of nanotechnology is the increasing of the leakage current S. Mukhopadhyay (2005), it tends to become the dominant element of the total power dissipation. Although scaling down the supply voltage even reduces the dynamic power dissipation, but it causes a linear increase in the propagation delay time, Kawagashi (1998). Consequently, specific technology parameters have to be changed appropriately in order to maintain the transistor speed, such as these parameters are: threshold voltage, thickness of the dioxide and the length of the transistor’s gate. The Sequential circuits are substantial components in VLSI designs; the most digital systems use sequential circuits to perform various memory functionalities. These circuits correspond to memory cells and flip-flops. Due to the input capacitance of the flip-flops and the capacitance of the clock lines, the energy consumed on the clock line is a significant component of the total power dissipation. It is a fact that the clock power dissipation ranges from 20% to 45% of the total power dissipation on a chip, and also 90% of it is consumed on the sequential circuits J. Seomun (2007) and Lang (2007). This gives the sequential circuits more attention to be investigated and analyzed in order to save power without compromising state integrity and performance. Generally, the most common techniques used to reduce the power dissipation are the low swing voltage technique, K. Seng (2001), the gated logic technique, T. Lang (1997), and the multi-threshold voltage technique, J. Kao (2000). The low swing voltage technique will not remain important for long time, since supply voltage itself is already reduced to less than 0.8V. The gated logic technique demands extra circuits to be inserted, these circuits occupies area and consume extra power which should be considered when the total power dissipation is calculated. The multi-threshold voltage technique suffers from the increased value of the sub- threshold current while also the noise margins are worsen due to the reduction of the threshold voltage.