CSD-RNS-based Single Constant Multipliers Evangelos Vassalos & Dimitris Bakalis Received: 7 September 2009 / Revised: 21 October 2010 / Accepted: 21 October 2010 / Published online: 4 November 2010 # Springer Science+Business Media, LLC 2010 Abstract Architectures for designing single constant multi- pliers in Residue Number System (RNS) for moduli of the 2 n -1, 2 n and 2 n +1 forms are introduced with the constant operand being recoded in Signed-Digit representation. Two methodologies are proposed. In the first one a straightfor- ward implementation of the shift-and-add algorithm is adopted, while in the second one a graph-based approach is used. Both methodologies result in circuits that are shown to be efficient in terms of area and delay. Keywords Residue number system . Modulo {2 n -1, 2 n ,2 n +1} . Signed-digit number system . Canonical signed-digit representation . Constant multiplication 1 Introduction The Residue Number System (RNS) [1, 2] is a non- weighted, carry-free, number system that is frequently employed in the design of special-purpose hardware units, such as digital signal processors [3], Discrete Cosine Transform (DCT) processors [4], Wavelet processors [5], Finite Impulse Response (FIR) filters [6], real-time image processing units [7], and communication components [8, 9]. An RNS is characterized by a set {m 1 , m 2 ,...,m p } of P moduli that are pair wise relatively prime. An integer A, with 0 ≤ A < M, where M ¼ m 1  m 2  ...  m p , has a unique representation in the RNS given by the set of residues A ¼ a 1 ; a 2 ; ... ; a p   , where a i = A mod m i . The RNS offers significant speedup over the binary system, due to fact that arithmetic operations (mainly additions, sub- tractions and multiplications) are carried out independently in each modulo channel. RNSs built on moduli of the 2 n ,2 n -1 and 2 n +1 forms have received significant attention [10, 11] due to the fact that the required circuits for the 2 n moduli can be straightforwardly derived from the corresponding non- RNS circuits by limiting the result to n bits, while adders and multipliers have been proposed for the 2 n ±1 moduli that can operate almost as fast as the non-RNS ones of the same operand widths. The 2 n +1 channel has to deal with operands that are (n +1)-bits wide compared to the n-bit wide operands of the modulo 2 n -1 and the modulo 2 n channels. Leibowitz [12] introduced the diminished-one representation where each number is represented decreased by one compared to its normal representation and all arithmetic operations are inhibited for a zero input operand since the result in most cases can be straightforwardly derived. The diminished-one representation has the advan- tage that the computations in the modulo 2 n +1 channel are restricted to n bits leading to more efficient arithmetic units compared to the normal representation. The additional cost of converting from/to the diminished-one representation is in most cases small (an incrementer or a decrementer), while in some cases (e.g. in forward conversion) using the diminished-one representation leads to circuits with the same or better performance compared to those using the normal representation [13, 14]. A non-conventional, redundant number system that has received considerable attention is the Signed-Digit (SD) number system [15–17]. In radix-2 SD number system, a {-1, 0, 1} digit set is used and an n-digit integer E. Vassalos (*) : D. Bakalis Electronics Laboratory, Physics Department, University of Patras, Patras, Greece e-mail: vassalos@upatras.gr D. Bakalis e-mail: bakalis@physics.upatras.gr J Sign Process Syst (2012) 67:255–268 DOI 10.1007/s11265-010-0552-z