An Efficient Implementation of High Speed Modified Booth Encoder for Floating Point Signed & Unsigned Numbers P.V.Krishna Mohan Gupta 1 , Ch.S.V.Maruthi Rao 2 , G.R. Padmini 3 , 1 M.Tech (DSCE), Sreyas Institutite of Engineering & Technology, Hyderabad, 2 Associate Professor, Sreyas Institutite of Engineering & Technology, Hyderabad, 3 Associate Professor, Vasavi College of Engineering, Hyderabad, Abstract---Multiplication is an important fundamental function in arithmetic operations. It can be performed with the help of different multipliers using different techniques. In this paper we focus on an efficient implementation of an IEEE 754 single precision floating point multiplier with signed and unsigned numbers. The multiplier implementation in floating point multiplication is done by Modified Booth Encoding (MBE) multiplier to reduce the partial products by half. The multiplier takes care of overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. By using MBE multiplier we increases the speed of multiplication, reduces the power dissipation and cost of a system. The proposed multiplier will be designed and verified using Modelsim with Verilog HDL. Xilinx is used for synthesis. Keywords-floating point multiplication, Array Multiplier, MBE, Partial Products, overflow and underflow I. INTRODUCTION Today the main applications of floating point numbers are in the field of medical imaging, biometrics, motion capture and audio applications. Since multiplication dominates the execution time of most DSP algorithms, there is a need of high speed multiplier with more accuracy. Reducing the time delay and power consumption are very essential requirements for many applications. Floating Point Numbers: The term floating point is derived from the fact that there is no fixed number of digits before and after the decimal point, that is, the decimal point can float. The Institute of Electrical and Electronics Engineers (IEEE) sponsored a standard format for 32-bit and larger floating point numbers, known as IEEE 754 standard [1]. This paper presents a new floating point multiplier which operates on single-precision floating point. The conventional floating point multipliers use Array multiplier for Mantissa multiplication [2]. In this paper we presents a Modified Booth Encoder (MBE) multiplier [3][4] for Significand or Mantissa multiplication, which reduces the partial products by half, to achieve speed of operation and reduces the time delay[6].Normal MBE multiplier having Carry Save Adder(CSA) for partial product addition[5], here in this floating point multiplier we proposed Ripple Carry Adder(RCA) to reduce the complexity of the circuit and complicated more number of bit addition. This paper is organized as follows: In section I (B) mainly concentrated on Single Precision floating point numbers, section II focuses on floating point algorithm, section III concentrate on different multiplication methods[7][8], section IV looking for hardware of floating point multiplier(Block diagram), section V contains the exponent result on overflow or underflow and final sectional explains synthesis results and conclusions of this project A. Floating Point Arithmetic The IEEE 754 [1] standard is the most widely used standard for floating point computation, and is followed by many CPU implementation. The standard defines formats for representing floating point number (including + zero and denormals) and special values (infinities and NaNs) together with a set of floating point operations. IEEE 754[1] specifies four formats for representing floating point values: single- precision (32-bit), double-precision (64-bit), single-extended precision (≥ 43-bit, not commonly used) and double extended precision (≥ 79-bit, usually implemented with 80 bits). B. Single Precision Floating point Numbers Thus, a total of 32 bits is needed for single-precision number representation. To achieve a bias equal to 2 n-1 -1 is added to the actual exponent in order to obtain the stored exponent. This equal 127 for an 8-bit exponent of the single precision format. The addition of bias allows the use of an exponent in the range from -126 to +127. The single precision format offers a range from 2 -126 to2 +127 . Fig. 1 shows the IEEE 754 single precision binary format representation; it consists of a one bit sign (S), an eight bit exponent (E), and a twenty three bit fraction (M or Mantissa). An extra bit is added to the fraction to form what is called the significand 1 . If the exponent is greater than 0 and smaller than 255, and there is 1 in the MSB of the significand then the number is said to be a normalized number; in this case the real number is represented by (1) Fig. 1. IEEE single precision floating point format 1867 International Journal of Engineering Research & Technology (IJERT) Vol. 2 Issue 8, August - 2013 ISSN: 2278-0181 www.ijert.org IJERTV2IS80531