IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 11, NOVEMBER 1996 1831 A CMOS 6-b, 200 MSample/s, 3 V-Supply A/D Converter for a PRML Read Channel LSI Sanroku Tsukamoto, Ian Dedic, Toshiaki Endo, Kazu-yoshi Kikuta, Kunihiko Goto, and Osamu Kobayashi Abstract— A CMOS 6-b, 200 MSample/s, (MS/s) flash A/D converter (ADC) with 3 V power supply has been developed for a mixed-signal partial-response maximum likelihood (PRML) read channel LSI. In a CMOS flash ADC with chopper comparators, all comparators are auto-zeroed prior to each conversion. As a result, half of the available comparison time is spent auto- zeroing. To improve conversion rate and performance when included in a mixed-signal LSI, the auto-zeroing rate was re- duced using a newly developed “interleaved auto-zeroing” (IAZ) architecture. Less frequent auto-zeroing also reduces kickback noise to the analog input and reference resistor string and power supply noise. In addition, the comparator output-swing is limited to improve recovery from large overdrives by adding diode connected transistors. This “output-swing limiting comparator” (OLC) improved the response to high frequency analog inputs. A conversion rate of 200 MS/s was achieved in the PRML read channel LSI using the IAZ architecture and OLC. This ADC was fabricated with single poly-Si, double-Metal, 0.5- m CMOS technology. I. INTRODUCTION R ECENTLY developed hard disk drives (HDD) use partial-response maximum likelihood (PRML) signal processing to increase recording density. There is a require- ment for high-speed A/D converter (ADC), and the ADC is one of the most important elements. The typical architecture of a PRML read channel LSI is shown in Fig. 1. Because of high speed operation, most of the ADC’s are bipolar or Bi-CMOS, [1]. Conventional CMOS ADC’s have rather slow conversion rates of about 100 MS/s [2]–[4]. In many cases, chopper comparators have been applied to CMOS flash ADC’s. Pure differential comparators, without auto-zeroing, are not suitable for more than 8-b resolution CMOS flash or subranging ADC’s because of large differences between comparator offset volt- ages [5], [6]. For CMOS flash ADC’s, auto-zeroing is required to compensate for mismatches of elements [7]. In many cases, inverter chopper comparators are adopted, for the reasons of simplicity of the circuit [8], [9]. However, conventional CMOS flash ADC’s with inverter chopper comparators were not suitable for mixed-signal LSI’s because of insufficient tolerance to noises [10], [11]. Manuscript received April 3, 1996; revised July 30, 1996. S. Tsukamoto, T. Endo, and K. Kikuta are with the Fujitsu VLSI Ltd., Kasugai, Aichi, Japan. I. Dedic is with the Fujitsu Microelectronics Limited, Maidenhead SL6 4BW U.K. K. Goto and O. Kobayashi are with the Fujitsu Ltd., Nakahara, Kawasaki, Kanagawa, Japan. Publisher Item Identifier S 0018-9200(96)07935-8. Fig. 1. Block diagram of PRML read channel LSI. Noises, kickback noise to analog input or reference re- sistor strings, and power supply noise are caused when the state transition of comparator occurs. Auto-zeroing of the chopper comparator occasionally and comparing the analog input continuously in the comparison state is very effective in reducing these noises. This also increases the conversion rate because the whole conversion cycle time is available for comparison [12]. But continuous A/D conversion is not possible, because conversion is prevented in the auto-zeroing period. This drawback restricts the application. When a conventional chopper comparator compares several times with one auto-zeroing, the response to high-frequency analog inputs will be degraded. Most chopper comparators are designed to recover from large input overdrives by auto- zeroing. Comparing several times with one auto-zeroing gives poorer high-frequency input response than auto-zeroing before each comparison. It is desirable to reduce the auto-zeroing rate without needing an extra auto-zeroing period for the whole ADC and to design a high-speed comparator which compares several times with one auto-zeroing. Both goals were achieved using a newly developed “interleaved auto-zeroing” (IAZ) architecture and “output-swing limiting comparator” (OLC). The ADC architecture IAZ is described in Section II, and the comparator circuit is described in Section III. II. ADC ARCHITECTURE A. Conventional Implementation A chopper comparator [Fig. 2(a) and (b)] has been generally used in the CMOS flash and subranging ADC’s. The operation of this comparator is to let the inverting input and the output of amplifier be short-circuited by turning on the switch, and bias its threshold to compensate for asymmetry of elements (auto-zeroing). At the same time, reference voltage “ ” is 0018–9200/96$05.00  1996 IEEE