Letter Thin film SOI HBT: A study of the effect of substrate bias on the electrical characteristics S. Fregonese a, * , G. Avenier a,b , C. Maneux a , A. Chantre a , T. Zimmer a a Laboratoire de Microe ´lectronique IXL, CNRS UMR 5818, Bordeaux 1 University, 33405 Talence, France b ST Microelectronics, 850 rue Jean Monnet, BP 16, F-38 926 Crolles Cedex, France Received 30 May 2006; received in revised form 21 September 2006; accepted 30 September 2006 The review of this paper was arranged by Prof. S. Cristoloveanu 1. Introduction To date, the key argument of SOI CMOS technology for RF/MMIC applications is the full electrical isolation which allows a better use of passive components. Likewise, the lower substrate parasitic capacitance, the reduction in sig- nal crosstalk and the elimination of latch-up phenomena contribute to make this technology attractive and reliable. SiGe BiCMOS is often referred to as a platform technology for wireless applications. Although, the maturity of SiGe SOI HBTs has not yet reached the SOI CMOS one, prom- ising performances have been demonstrated [1–5]. Actu- ally, Chen et al. [4] present a breakdown voltage, BV CE0 of around 4.7 V and a transit frequency, f T around 37 GHz. Likewise, Avenier et al. [5] present different HBT designs, the high voltage device characteristics are BV CE0 = 6.4 V, f T = 35 GHz and f max = 134 GHz, while the high speed device characteristics are BV CE0 = 1.8 V, f T = 86 GHz and f max of 149 GHz. For these HBT technol- ogies, the first step towards circuit design is the definition of an accurate device model. The folded collector structure of the partially depleted SOI layer induces HBT operation noticeably different compared with bulk Si HBT character- istics. This HBT operation is analysed in [6] and a compact model is derived. The second major difference with bulk devices is the substrate bias effects which depend on buried oxide thickness, collector thickness and especially collector doping. Substrate bias effects increase with the decrease of collector doping. In [4] a phenomenological study of sub- strate bias effects in SOI HBTs has been presented. It is based on 2-D MEDICI simulation and investigates the effect of substrate bias on collector resistance, avalanche multiplication phenomena, self-heating and device reliabil- ity while our paper investigates the impact of substrate bias on transit time from an analytical point of view and under the perspective of modelling and parameter extraction pur- poses. The underlying equations are developed. So, the substrate bias effect is directly linked to its physical origin and electrical behavior. This paper is organised as follows: Section 2 focuses on the physical mechanisms occurring in an SOI HBT when applying a substrate bias. Section 3 presents the impact of substrate bias on electrical characteristics such as transit frequency and gives the corresponding analytical relation- ships. Section 4 concludes. 2. Physical impact of substrate bias Physical simulations using ISE software [7] were com- puted to quantify the underlying physics and to develop the analytical relationships. The collector-oxide-substrate structure (see Fig. 1) of the thin film SOI HBT acts as a PIN junction capacitor. Biasing the substrate node, some free carriers move on both sides of the oxide. Depending on collector-substrate bias, V S , an accumulation or a deple- tion of electrons in the collector is observed next to the col- lector-oxide interface. The Fig. 2 shows that a direct forward bias of V S (>0) involves an electron accumulation, while a negative bias implies a carrier depletion at the collec- tor-oxide interface. This carrier depletion or accumulation acts as a modification of the effective average collector 0038-1101/$ - see front matter Ó 2006 Published by Elsevier Ltd. doi:10.1016/j.sse.2006.09.019 * Corresponding author. Tel.: +33 5 4000 2816; fax: +33 5 56371545. E-mail addresses: fregonese@ixl.fr, s.fregonese@tudelft.nl (S. Frego- nese). www.elsevier.com/locate/sse Solid-State Electronics 50 (2006) 1673–1676