Nuclear Instruments and Methods in Physics Research A 473 (2001) 140–145 An introduction to deep submicron CMOS for vertex applications M. Campbell*, G. Anelli, E. Cantatore 1 , F. Faccio, E.H.M. Heijne, P. Jarron, J.-C. Santiard, W. Snoeys, K. Wyllie CERN, EP division, 1211 Geneva 23, Switzerland Abstract Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed. r 2001 Published by Elsevier Science B.V. Keywords: CMOS; Readout electronics; Vertex detectors 1. Introduction The development of readout electronics for the vertex detectors of the future LHC detectors is progressing rapidly. Custom designed ASICs have become crucial components of these systems and microelectronics is now recognised as a key enabling technology in experimental High Energy Physics (HEP). This activity runs concur- rently with the continuous shrinking of gate lengths in commercial CMOS processes. This paper discusses briefly the motivations for this trend in commercial CMOS and explores the implications of the trend for vertex detector readout electronics. Radiation hardness is an important issue for these applications. Radiation effects in deep sub-micron CMOS are reviewed briefly. Special layout and circuit topologies can be used to design radiation tolerant readout chips. The techniques used are discussed. More- over, CMOS component density is a critical parameter in determining the cell size of pixel detectors which form the inner layers of most of the trackers. It will be shown that sufficiently small pixel sizes (50–100 mmÞ can still be achieved in spite of the area penalty incurred in using radiation tolerant design techniques. Some of the implications of future device scaling will be discussed. This will force designers to rethink circuit topologies which are suitable to the much reduced power supplies of the future very deep sub-micron processes. *Corresponding author. E-mail address: michael.campbell@cern.ch (M. Campbell). 1 Now at Philips Research Nat. Lab., Prof. Holstlaan 4 (WAY 51), 5656AA Eindhoven, The Netherlands. 0168-9002/01/$-see front matter r 2001 Published by Elsevier Science B.V. PII:S0168-9002(01)01135-4