IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 5, NO. 2, MARCH/APRIL 1999 353 Application of Networking Concepts to Optoelectronic Multiprocessor Architectures James Rorie, Philippe J. Marchand, Member, IEEE, Jeremy Ekman, Fouad E. Kiamilev, Member, IEEE, and Sadik C. Esener, Member, IEEE Abstract—This paper describes an approach to creating high- speed multiprocessor architectures involving free-space optical interconnects using knowledge gained from the analysis of tra- ditional network topologies. Development of an architectural specification through identification of the components of a func- tional description and mapping them to an appropriate network model is presented. By applying these techniques, the designer has the advantage of field tested solutions to the problems that occur in the development of complex, hybrid, hierarchal, optoelectronic multiprocessor architectures, and protocols. Index Terms—Architecture, optoelectronic, FFT, stacking, VC- SEL, VLSI. I. INTRODUCTION D EVELOPING systems involving optoelectronic compo- nents can present a number of challenges to the hardware designer. There are a multitude of issues that must be ad- dressed when exchanging data between low-speed electrical buses and the higher speed optical environment. These hybrid architectures are further complicated when hierarchal design strategies are applied. In an attempt to reduce optoelectronic multiprocessor de- sign complexities, concepts from related fields have been applied. Among these fields, network architecture bears the greatest similarity. Many networking concepts have been ap- plied successfully in the area of parallel processing [1] and optoelectronic systems [2], [3]. Hence, we have adopted a network architecture model for the design of optoelectronic multiprocessor systems. A. Impetus The device technologies used in the optical area exist mainly in small production runs; therefore, their price is considerable relative to other technologies. To maximize capital resources during the development cycle, an attempt must be made to reduce the number of prototypes required. This requires Manuscript received November 9, 1998; revised March 15, 1999. This work was supported by the Defense Advanced Research Projects Agency (DARPA) and by the Air Force Research Laboratory under agreement number F30602- 97-2-0122. J. Rorie, J. Ekman, and F. Kiamilev are with the Department of Electrical- Computer Engineering, University of North Carolina-Charlotte, Charlotte, NC 28223 USA. P. Marchand and S. Esener are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA. Publisher Item Identifier S 1077-260X(99)05475-1. extensive simulation of designs that are developed by using sound operational concepts. In order to accomplish these goals within the time con- straints set for a project, rapid prototyping techniques also need to be applied. But these techniques only speed the actual implementation of the design. Other techniques need to be utilized to quickly develop the architectural specifications. In this paper, we present a technique for using network models as guidelines for developing high-speed, optoelectronic architectures. Previous work in optoelectronic multiprocessor systems has focused on using optical interconnects to imple- ment the interconnection network [10]–[12] and evaluation of proposed optoelectronic multiprocessor architectures [13]. By selecting an example that possesses strong functional relationships, problems that occur in development can be addressed through simple analysis. The result is a structured approach to optoelectronic multiprocessor design. II. MAPPING FUNCTIONAL SPECIFICATION TO NETWORK TOPOLOGY The first step to in applying this approach is to find an appropriate real world model for the proposed system and map these concepts to an architectural specification. The critical decision involved in applying the network topological concepts is the selection of an appropriate model. This is accomplished through a careful examination of the functional specification. A. The 3-D OESP Architecture The three-dimensional (3-D) optoelectronic stacked proces- sor (OESP) project consists of the development of a custom system architecture based around vertical chip stacking tech- nology. This technology combines individual very large scale integrated (VLSI) die in a 3-D fashion to form a cubic device. These stacks are then used with optical interconnects to create a high-speed, high-density computational platform. 1 The architecture needs to support the calculation of two-dimensional (2-D) fast Fourier transforms (FFT’s) and other digital signal processing functions using vertical- cavity surface-emitting laser (VCSEL) based free-space optical interconnects (FSOI’s) for communication between planes (die) and stacks [15]. Major architectural points are the development of reliable high-speed serial link and an interprocessor communication protocol. This protocol must account for the unique requirements of the FSOI’s 1 Irvine Sensors Corporation, Costa Mesa, CA 92626 USA. 1077–260X/99$10.00  1999 IEEE