A Prototype 3D Optically Interconnected Neural Network zyxw GOKCE YAYLA, STUDENT MEMBER, IEEE, ASHOK V. KRISHNAMOORTHY, MEMBER, IEEE, GARY C. MARSDEN, AND SADIK C. ESENER zyxwvu Invited Paper zyxwvutsrqp We report the implementation of a protoope three-dimensional (30) optoelectronic neural network that combines free-space optical interconnects with silicon-VLSI-based optoelectronic circuits. The prototype system consists of a 16-node input, 4-neuron hidden, and a single-neuron output layer, where the denser input-to-hidden-layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed over an optoelectronic neural network chip through space-invariant holographic optical interconnects. Optical interconnections provide negligible fan-out delay and allow mmpart, purely on-chip electronic H-tree type fan-in structure. The small protogpe system achieves a measured 8-bit electronic fan-in precision and a calculated maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off-system and was shown to distinguish any vertical line from any horizontal one in an image of 4 zyxwvutsrqpo x 4 pixels. New, more efficient light detector and small-area analog synapse circuits and denser optoelectronic neuron layouts are proposed to scale up the system. A high-speed, feed-forward optoelectronic synapse implementation density of up to I04/cm2 seems feasible using new synapse design. A scaling analysis of the system shows that the optically interconnected neural network implementation can provide higher fan-in speed and lower power consumption characteristics than a purely electronic, crossbar-based neural network implementation. I. INTRODUCTION Applications of neural network techniques to large-size problems necessitate massively parallel neural network hardware implementations. Performance of such large- scale, globally connected VLSI systems, however, is severely limited by the long interconnection line lengths Manuscript received December zyxwvutsrqpon 1, 1993; revised July 8, 1994. G. Yayla and E. C. Esener are with the Department of Electrical and Computer Engineering, University of California-San Diego, La Jolla, CA A. V. Krishnamoorthy was with the Department of Electrical and Computer Engineering, University of California-San Diego, La Jolla, CA 92093-0407 USA. He is now with AT&T Bell Laboratories, Rm. 4b-523, Holmdel, NJ 07733 USA. G. C. Marsden was with the Department of Electrical and Computer Engineering, University of CaliforniaSan Diego, La Jolla, CA 92093- 0407 USA. He is now a Consultant at 9959 Adieta Blvd. #23, Dallas, TX 75243 USA. 92093-0407 USA. IEEE Log Number 9405126. between processing elements. While on-chip communica- tion delays increase linearly with interconnection lengths [l], inter-chip communications suffer from the large off- chip parasitic capacitances which dramatically increase interconnection delays [2] and power consumption. Restrictions of long electrical interconnections in VLSI systems can be alleviated by using optical interconnections for global communication [3]. If electronic processing elements (PE’s) are provided with optical 1/0 capability, the third dimension, normal to the proccssing plane, can be used for global optical interconnections. Owing to the high speed of light propagation, optical interconnection delay is practically independent of the interconnection length. For interconnections longer than a certain break-even line length, optical interconnections also have lower energy requirements due to the lower interconnection capacitances and time constants [4]. As will be seen in Section 111, the use of the third dimension for optical communication provides two-dimensional (2D) I/O to/from the PE’s, which enables efficient, 2D (square or close to square shaped) PE layouts with minimized intra-PE electrical connections zyx [5]. This reduces on-chip delays and power consumption and avoids the limitations of off-chip electrical interconnections, since intra-PE connections are purely on-chip as long as an entire PE can fit on a single chip. These considerations there- fore favor optically interconnected 3D VLSI systems to implement massively parallel, connectionist architectures. In this paper, we report the implementation of a prototype 3D optoelectronic neural system and discuss its scaling performance. In Section 11, we present a brief discussion on how optical interconnects can be efficiently used in a neural network implementation. In Section 111, a review of the Dual-Scale Topology Optoelectronic Processor (D- STOP) architecture is given [6]. Section IV is devoted to the prototype neural system implementation: description of the system, experimental results on light transmitter and detector performances, mixed-signal optoelectronic neural circuits, and optical interconnection system are presented. 0018-9219/94$04.M) zyxwvutsrq 0 1994 IEEE PROCEEDINGS OF THE IEEE, VOL. 82, NO. 11, NOVEMBER 1994 1749