A core generator for arithmetic cores and testing structures with a network interface q D. Bakalis a,c, * , K.D. Adaos a , D. Lymperopoulos a , M. Bellos a , H.T. Vergos a , G.Ph. Alexiou a,b , D. Nikolos a,b a Computer Engineering and Informatics Department, University of Patras, 265 00 Patras, Greece b Research Academic Computer Technology Institute, 61 Riga Feraiou Str., 262 21 Patras, Greece c Electronics Laboratory, Department of Physics, University of Patras, 265 00 Patras, Greece Received 7 October 2002; received in revised form 30 September 2003; accepted 16 December 2004 Available online 13 June 2005 Abstract We present Eudoxus, a tool for generation of architectural variants for arithmetic soft cores and testing structures targeting a wide variety of functions, operand sizes and architectures. Eudoxus produces structural and synthesizable VHDL and/or Verilog descriptions for: (a) several arithmetic operations including addition, subtraction, multiplication, division, squaring, square rooting and shifting, and (b) several testing structures that can be used as test pattern gen- erators and test response compactors. Interaction with the user is made through a network interface. Since the end user is presented with a variety of unencrypted structural cores, each one describing an architecture with its own area, delay and power characteristics, he can choose the one that best fits his specific needs which he can further optimize or customize. Therefore, designs utilizing these cores are completed in less time and with less effort. Ó 2005 Elsevier B.V. All rights reserved. 1. Introduction Engineers that deal with System-on-a-Chip (SoC) design, face the challenge to integrate a rich set of features in a single piece of silicon, with high performance requirements, on progressively shorter product life cycles in order to achieve todayÕs strict time-to-market goals [1,2]. To cope with these challenges, a block-based approach, that emphasizes design reuse, becomes necessary. 1383-7621/$ - see front matter Ó 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.sysarc.2004.12.006 q Based on ‘‘EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores’’, by D. Bakalis, K.D. Adaos, D. Lymperopoulos, G.Ph. Alexiou and D. Nikolos, which appeared in Proceedings of 12th IEEE International Workshop on Rapid System Prototyping, Monterey, CA, USA, pp. 182– 187. Ó 2001 IEEE. * Corresponding author. Tel.: +30 2610 996287; fax: +30 2610 997456. E-mail address: bakalis@physics.upatras.gr (D. Bakalis). Journal of Systems Architecture 52 (2006) 1–12 www.elsevier.com/locate/sysarc