FINDING DOUBLE EULER TRAILS OF PLANAR GRAPHS IN LINEAR TIME ∗ ZHI-ZHONG CHEN † , XIN HE ‡ , AND CHUN-HSI HUANG § SIAM J. COMPUT. c  2002 Society for Industrial and Applied Mathematics Vol. 31, No. 4, pp. 1255–1285 Abstract. This paper answers an open question in the design of complimentary metal-oxide semiconductor VLSI circuits. The question asks whether a polynomial-time algorithm can decide if a given planar graph has a plane embedding E such that E has an Euler trail P = e 1 e 2 ...em and its dual graph has an Euler trail P * = e * 1 e * 2 ...e * m , where e * i is the dual edge of e i for i =1, 2,...,m. This paper answers this question in the affirmative by presenting a linear-time algorithm. Key words. planar graph, dual graph, Euler trail AMS subject classifications. 05C45, 05C85, 05C90, 68Q35, 68R10 PII. S0097539799354321 1. Introduction. Throughout this paper, a graph may have multiple edges but never has loops. A graph G is planar if it can be drawn on the plane so that the edges intersect only at their end vertices. Such a drawing is called an embedding of G.A plane graph is a planar graph with a fixed embedding. A two-terminal graph 1 (TTG) G =(V,E) is a plane graph with a pair (s, t) of specified vertices on the outer face such that adding the edge {s, t} to G yields a biconnected plane graph [4, 6]. We call s the source of G and t the sink of G. We also call s and t the poles of G and the other vertices the nonpoles of G. As in previous studies, we visualize G in such a way that s is at the South Pole while t is at the North Pole. The poles of G divide the boundary of the outer face into two paths, which are called the west side and the east side of G, respectively. In the dual graph G ∗ = (V ∗ ,E ∗ ) of G, there are two dual vertices s ∗ and t ∗ corresponding to the outer face of G. The dual edges incident to s ∗ (respectively, t ∗ ) in G ∗ correspond to the edges on the west (respectively, east) side of G. Figure 1.1(2) shows a TTG G and its dual G ∗ . G ∗ is a TTG with source s ∗ and sink t ∗ [12]. In complimentary metal-oxide semiconductor (CMOS) technology, the basic lay- out of a circuit C of transistors on a VLSI chip uses two rows of transistors: A row of pMOS transistors is laid out next to a row of nMOS transistors [13]. The circuit C can be represented by a pair of TTGs: The p-transistors are represented by G, where each edge of G represents a p-transistor. The n-transistors are represented by the dual graph G ∗ of G, where each edge of G ∗ represents an n-transistor. In Figure 1.1, (1) shows a circuit implementing the Boolean function z =¯ e ∧ (¯ a ∨ ¯ b) ∧ (¯ c ∨ ¯ d), and (2) shows the corresponding TTGs G and G ∗ . * Received by the editors April 2, 1999; accepted for publication (in revised form) December 4, 2001; published electronically May 8, 2002. A preliminary version of this work was presented at the 40th Annual Symposium on Foundations of Computer Science, 1999, New York City, New York. http://www.siam.org/journals/sicomp/31-4/35432.html † Department of Mathematical Sciences, Tokyo Denki University, Hatoyama, Saitama 350-0394, Japan (chen@r.dendai.ac.jp). ‡ Department of Computer Science and Engineering, State University of New York at Buffalo, Buffalo, NY 14260 (xinhe@cse.buffalo.edu). This author’s research was supported in part by NSF grant CCR-9912418. § Department of Computer Science and Engineering, University of Connecticut, Storrs, CT 06269 (huang@cse.uconn.edu). 1 Previously called planar st-graphs and treated as digraphs just for convenience. 1255