(IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 8, No. 5, 2017 438 | Page www.ijacsa.thesai.org Miniaturisation of a 2-Bits Reflection Phase Shifter for Phased Array Antenna based on Experimental Realisation Mariem Mabrouki Unit of Research in High Frequency Electronic Circuits and Systems, Faculty of Mathematical, Physical and Natural Sciences of Tunis, Tunis El Manar University, Campus Universities Tunis - El Manar, 2092 Tunis, Tunisia Bassem Jmai Unit of Research in High Frequency Electronic Circuits and Systems, Faculty of Mathematical, Physical and Natural Sciences of Tunis, Tunis El Manar University, Campus Universities Tunis - El Manar, 2092 Tunis, Tunisia Ridha ghayoula Unit of Research in High Frequency Electronic Circuits and Systems, Faculty of Mathematical, Physical and Natural Sciences of Tunis, Tunis El Manar University, Campus Universities Tunis - El Manar, 2092 Tunis, Tunisia Ali. Gharsallah Unit of Research in High Frequency Electronic Circuits and Systems, Faculty of Mathematical, Physical and Natural Sciences of Tunis, Tunis El Manar University, Campus Universities Tunis - El Manar, 2092 Tunis, Tunisia Abstract—In this paper, a controllable reflection type Phase Shifter (PS) is designed, simulated and implemented. The structure of the 2-bits PS consists of branch line coupler, delay lines and six GaAs FET switches controlled in pair. The phase shifting is achieved by turning ON one pair of switches. The circuit design is fabricated using FR4 substrate with dielectric constant equal to 4.7. The size of the realised circuit is 7cm×2.8cm. To reduce this size, two methods are used. First, shortened quarter-wave length transmission line in T model is employed to develop a compact branch-line coupler. Second, a loaded line with capacitor is used to reduce the dimension of delays lines. The two methods are combined to realise a PS with compact size equal to 4.5cm×1.96cm. Keywords—Reflection type PS; FET switch; Branch line coupler; Semiconductors technology I. INTRODUCTION The PS is the key component in phased array antennas used for electronic beam steering. Using digital PS based on semiconductors technology, we can realise an accurate scanning of beam former and a good compatibility with the computer control. Four classical design topologies are developed to realise digital PS, they are: the switched line, the loaded line, the switched low-pass / high-pass and the reflection theories, each of these methods has its own limitation [1-2]. The topology reflection achieves a low insertion loss and a low phase error, but it presents a poor match over a large bandwidth Several PSs operating in the L and S band frequency are developed and discussed in the literature. In [3], a reflection type PS characterized by an ultra-band is developed. The structure of the PS is composed of 3 dB hybrid coupler and a pair of novel reflective terminating circuit. The 180° and 90° MMIC PS have demonstrated a phase of 187±7° over 0.5-20 GHz and a phase of 93°±7° over 7-12 GHz. Another reflection type PSs are presented in [4]. The PSs are implemented at 2.45 GHz in a 0.18 μm CMOS technology. So, an impedance transformed π resonated varactor network is employed to provide 360° phase rang. The measured results of the two PSs show a phase shift range of 120° with insertion losses 5.6 ± 1.6 dB and a phase range larger than 340° with the insertion losses of 10.6±2 dB over the band 2.44-2.55 GHz. In [5], another reflection type PS is developed, achieving a phase shift over 400° between 1.95 and 2.15 GHz. The circuit is composed of 3 dB hybrid coupler and reflection loads. Measurement results show insertion loss less than 4 dB for 400° phase shift. Based on the previously mentioned proposals, we suggest in this work a design and the according implementation of the 2-bits reflection type PS operating at the frequency 2.4 GHz for phased array antennas. The proposed structure provides four different phase shifts. Based on the experimental realisation, we show the major drawbacks of our structure which are mainly related to its big size. Therefore, in a second part of this work, we propose a miniaturised version of the PS and address the corresponding simulation results. This paper is composed of four sections: Section 2 demonstrates our proposed of the 2-bits PS design, simulation, and corresponding implementation results. Section 3 demonstrates our optimisation in size version of the PS and illustrates the corresponding simulation results with ADS. Section 4 describes 2-bits miniaturised PS design and simulation. This paper is enclosed by Section 5 that is the conclusion and the perspectives.