2040 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006 Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate Charlotte Soens, Member, IEEE, Geert Van der Plas, Member, IEEE, Mustafa Badaroglu, Member, IEEE, Piet Wambacq, Member, IEEE, Stéphane Donnay, Member, IEEE, Yves Rolain, Fellow, IEEE, and Maarten Kuijk, Member, IEEE Abstract—Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degrada- tion of LC tank VCOs. The proposed linearized model is fast to de- rive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a de- sign with a p /n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18 m 3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model ac- curately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the pro- posed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring. Index Terms—CMOS integrated circuits, crosstalk, mixed- signal integrated circuits, modeling, voltage-controlled oscillator. I. INTRODUCTION A N IMPORTANT problem that arises during the design of a single-chip mixed-signal radio is the crosstalk from dig- ital to analog. Simulation of this crosstalk at the circuit level for large systems-on-chip (SoCs) does not provide the necessary in- sight to resolve it. Moreover, performing circuit simulations to investigate the crosstalk in a large SoC is not a workable solu- tion. First, the number of digital gates is so large that it is not practical to include them in analog circuit simulations. In addi- tion, the crosstalk occurs via the silicon substrate, the printed circuit board (PCB), the bonding wires, the package, and via Manuscript received September 30, 2005; revised March 20, 2006. This work was supported in part by the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Flanders). C. Soens is with IMEC, 3001 Leuven, Belgium, and also with the Department ELEC-ETRO, Vrije Universiteit Brussel (VUB), Belgium, and the IWT (e-mail: soens@imec.be). G. Van der Plas, M. Badaroglu, and S. Donnay are with IMEC, 3001 Leuven, Belgium. P. Wambacq and M. Kuijk are with IMEC, 3001 Leuven, Belgium, and also with the Vrije Universiteit Brussel (VUB), Belgium. Y. Rolain is with the Vrije Universiteit Brussel (VUB), Belgium. Digital Object Identifier 10.1109/JSSC.2006.880595 the ground and supply lines. All these parasitic paths have to be included in the circuit simulations as well, resulting in ex- tremely large simulation models. Analysis at a higher level of abstraction is more practical and gives much more insight in the coupling mechanisms. The problem of reducing the impact of substrate noise on analog/RF circuits has already received much attention in liter- ature. Because of the lack of systematic and reliable simulation methods designers are left with an intuitive and ad hoc approach to solve the substrate noise coupling problems. For example, in the single-chip Bluetooth system of [1], the radio has been care- fully isolated with a 300 m wide p guard ring connected to ground with 13 low-impedance bumps. It is estimated that the isolation structure reduces substrate noise coupling by 25 dB at 2.5 GHz. Although the system is functional, it is not clear if this guard ring is performing as intended. Similarly, in [2] the inte- gration of a radio onto a Pentium die is investigated. A noise transfer function analysis reveals that the use of deep n-well biasing based isolation in conjunction with differential circuit design is sufficient for radio integration. However, no functional system has been built to verify this analysis. The biggest modeling challenge for substrate noise impact is in lightly-doped substrates which are nowadays used in almost any bulk CMOS technology. Unlike the epi-type substrates, modeled as a single equipotential node, lightly-doped sub- strates have to be modeled as a three-dimensional RC-mesh. Hence, propagation of noise in a lightly-doped substrate is a distributed and layout dependent phenomenon. Lightly-doped substrates are preferred for wireless applications because they offer high- inductors, and feature higher isolation. In [3], [4], and [5], macromodels for the generation of digital switching noise are presented and validated with measurements, both for epi-type and lightly-doped substrates. However, the prop- agation towards and resulting impact on analog/RF circuits is not included. Concerning the impact on analog circuits, mostly circuit level simulations ([6], LNA) and interpretation of measurements ([7], ADC) have been reported. Refs. [8] and [9] derive an analytical model for substrate noise impact on ring oscillators. The analytical model is validated for epi-type substrates only and does not include a model for the digital noise generation. Moreover, the analytical model does not provide much information on the exact coupling mechanisms. To the authors’ best knowledge, this work is the first to present a linearized physical model that successfully predicts both the substrate noise generation by a digital modem and the resulting 0018-9200/$20.00 © 2006 IEEE