A New Linear Delay Element With Self Calibration Afshin Seraj and Mohammad Maymandi-Nejad Electrical Engineering Department Ferdowsi University of Mashhad (FUM) Mashhad - Iran maymandi@um.ac.ir Manoj Sachdev Electrical and Computer Engineering Department University of Waterloo Waterloo - Canada Abstract—Linearity in Delay Element is an important factor in many applications such as Fully Digital Analog to Digital Converters, Delay-Locked-Loops and Voltage Controlled Oscillators. In this work, a new Delay Element is proposed in which the relationship between the input analog voltage and the delay between its input pulse and output pulse is highly linear within an analog voltage range of 0.9V and a delay range of 0.5ns-4.5ns. The proposed Delay Element has been simulated using H-spice with a supply voltage of 1.8V in the 0.18 um CMOS technology. A calibration mechanism based on feedback technique is also proposed which can be used to reduce the impact of PVT variations. Keywords—delay line; linear; delay locked loop; fully digital ADC; self calibration; PVT variations; I. INTRODUCTION The main function of a Delay Element (DE) is to convert a voltage (and/or current) into a delay between its input pulse (Clk in ) and its output pulse (Clk out ). Fig .1 illustrates the functioning of DE. Delay elements are used in many applications like DLL, PLL, fully digital ADCs, fully digital VCOs, etc [1]. In almost all these applications, a linear relationship between the input analog control signal and the delay is desirable. On the other hand, obtaining such a linear relationship is very difficult and almost all delay elements provide a limited input range in which the characteristic curve (delay versus input analog control voltage) is linear [2]. In [3],[4] and [5], signal conditioning technique is employed to design linear DEs. These DEs are then used to improve the performance of DLL. In [6] a DE with enhanced linearity is proposed. This DE manages to improve the signal to noise ratio of Fully Digital ADC while reducing its power consumption. Furthermore, [2] provides a thorough analysis of Fully Digital ADCs and the role of DE in them. This paper proposes a new DE which has a linear characteristic curve over a relatively large input voltage range. To achieve this linearity, A special signal conditioner is designed for a popular DE called Current Starved Delay Element (CSDE). The proposed DE is implemented in the 0.18 um CMOS technology and simulation results are provided in the following sections. In order to reduce the impact of process, temperature and voltage variations on the linearity of the DE, Fig. 1. The functioning of delay elements a self-calibration technique is also proposed. This paper is organized as follows. In II, the Current Starved delay element is reviewed for its dominant role in the proposed DE. Section III is allocated to the proposed delay element. Finally, in section IV we discuss the calibration technique which is specifically designed for the proposed DE to ensure its linearity under any PVT conditions. II. THE CURRENT STARVED DELAY ELEMENT The functioning of the Current Starved Delay Element(CSDE) is based on a current source charging or discharging a capacitor. A CSDE that works with the rising edge of the clock is shown in Fig. 2. The parasitic capacitors of transistors M4 and M5 form a capacitive load at the gate of M5. As initial condition, we assume that Clk in is initially 0V, which implies that the capacitive load is full and Clk out is 0V. As Clk in rises and equals power supply voltage (V DD ), transistor M2, which acts as a switch, turns on and transistor M3, which acts as a current source, starts discharging the capacitive load. Fig. 2. The Current Starved Delay Element (CSDE)