IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 2, JUNE 2009 147 Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks Andreas Kerber and Eduard Albert Cartier (Invited Paper) Abstract—It has been demonstrated that the introduction of HfO 2 /TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO 2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This contribution summarizes recent advances in the understanding of charge trapping and defect generation in HfO 2 /TiN gate stacks. This paper relates the electrical properties to the chemical/physical properties of the high-ε dielectric and discusses test procedures specifically tailored to quantify gate stack reliability of HfO 2 /TiN gate stacks. Index Terms—Bias temperature instability, dielectric break- down, HfO2, high-k, metal gate, MOSFETs, reliability, stress induced leakage current (SILC), TiN. I. I NTRODUCTION R ECENT technology papers have amply demonstrated the benefits arising from the introduction of HfO 2 as a high- ε dielectric and TiN as a metallic gate electrode into the gate stack of FETs for future CMOS technologies [1]–[4]. First, high-ε/metal gate stacks (referred to as “HK/MG stacks” in the following) substantially reduce gate leakage currents because a physically thicker HfO 2 film with thickness t HfO 2 can be used at the same SiO 2 Equivalent Oxide Thickness, EOT = ε SiO 2 /ε HfO 2 · t HfO 2 , where ε SiO 2 and ε HfO 2 are the dielectric constants of SiO 2 and HfO 2 , respectively. The suppression of gate leakage allows for EOT scaling to far less than 1 nm at acceptable gate leakage currents, provides the means to continue with traditional gate length scaling for performance improvements, and facilitates the reduction of the device pitch and the increase of the packing density in future CMOS gener- ations [5]. Manuscript received December 11, 2008; revised January 29, 2009. First published March 10, 2009; current version published June 5, 2009. This work was supported in part by the Research Alliance Teams at various IBM Research and Development facilities. A. Kerber is with the Advanced Micro Devices, Yorktown Heights, NY 10598 USA (e-mail: Andreas.Kerber@amd.com). E. A. Cartier is with the IBM Research Division, Yorktown Heights, NY 10598 USA (e-mail: ecartier@us.ibm.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TDMR.2009.2016954 Fig. 1. (a) Basic gate-stack structure of a FET using a high-ε dielectric and a metal gate electrode. The gate stacks also contains an interfacial SiO 2 layer and a poly-Si layer. (b) Schematics showing the energy band diagram for an nFET with a TiN/HfO 2 /SiO 2 dual-oxide gate stack at flatband conditions. (c) and (d) Schematic energy band diagrams for positive and negative gate bias, respectively. The arrows indicate (red) electron and (blue) hole tunneling currents. In addition to the many integration challenges arising from the introduction of deposited oxides instead of thermally grown SiO 2 , and the insertion of a metal gate layer between the poly- Si and the gate dielectric, new reliability concerns emerge. Many of these concerns are thought to be directly related to the properties of the newly introduced materials in the gate stack and the dual-layer structure of the gate dielectric. Several recent review articles cover various reliability issues [6]–[9]. In this contribution, we summarize recent progress in un- derstanding the electrical properties of HfO 2 /TiN-based FETs and introduce test and measurement procedures specifically tailored to capture the reliability aspects of these new gate stacks. We also discuss a number of reliability issues that need immediate attention to raise the comfort level with the use of established test procedures and methodologies for these tech- nologies with radically transformed gate stacks. Specifically, we will address Positive and the Negative Bias Temperature Instability (PBTI and NBTI), Stress-Induced Leakage Currents (SILC), and Time-Dependent Dielectric Breakdown (TDDB). II. EXPERIMENTAL Fig. 1(a) shows the cross section through a FET containing the new gate stack with a deposited high-ε dielectric and a metal gate electrode. As shown, the gate stack is depicted as a multilayer structure consisting of at least an Interfacial SiO 2 1530-4388/$25.00 © 2009 IEEE www.DownloadPaper.ir www.DownloadPaper.ir